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DSP汇编指令集


ADSP 汇编指令集

2004 年 11 月 16 日





一、SUMMARIZE ............................................................................1 1、QUICK LIST OF INSTRUCTIONS ....................................1 2、OVERVIEW .........................................................................4 3、INTRUCTION TYPES & NOTATION CONVENTIONS ..6 4、MULTIFUNCTION INSTRUCTIONS ................................8 4.1、ALU/MAC With Data & Program Memory Read ....8 4.2、Data & Program Memory Read ...............................10 4.3、Computation With Memory Read............................10 4.4、Computation With Memory Write ........................... 11 4.5、Computation With Data Register Move ..................12 5、ALU, MAC & SHIFTER INSTRUCTION ........................13 5.1、ALU Group ..............................................................13 5.2、MAC Group .............................................................14 5.3、Shifter Group ...........................................................14 6、MOVE: READ & WRITE ..................................................15 7、PROGRAM FLOW CONTROL ........................................16 8、MISCELLANEOUS INSTRUCTIONS .............................17 9、EXTRA CYCLE CONDITIONS........................................18 9.1、Multiple Off-Chip Memory Accesses......................18

9.2、Wait States ...............................................................19 9.3、SPORT Autobuffering & DMA ...............................19 10、INSTRUCTION SET SYNTAX.......................................20 10.1、Punctuation & Multifunction Instructions .............20 10.2、Syntax Notation Example ......................................20 10.3、Status Register Notation ........................................21 二、DSP INSTRUCTIONS .............................................................22 1. ADD/ADD with CARRY .....................................................22 2. SUBTRACT X-Y/SUBTRACT X-Y with BORROW.........24 3. SUBTRACT Y-X/ SUBTRACT Y-X with BORROW.........26 4. AND, OR, XOR ....................................................................28 5. TEST BIT,SET BIT,CLEAR BIT, TOGGLE BIT ................30 6. PASS/CLEAR .......................................................................32 7. NEGATE ...............................................................................34 8. NOT ......................................................................................36 9. ABSOLUTE VALUE ............................................................37 10. INCREMENT .....................................................................38 11. DECREMENT ....................................................................39 12. DIVIDE ...............................................................................40 13. GENERATE ALU STATUS ...............................................43 14. MULTIPLY .........................................................................44 15. MULTIPLY/ACCUMULATE ............................................47

16. MULTIPLY/SUBTRACT ...................................................49 17. CLEAR ...............................................................................52 18. TRANSFER MR .................................................................53 19. CONDITIONAL MR STATURATION ..............................55 20. ARITHMMETIC SHIFT ....................................................56 21. LOGICAL SHIFT ...............................................................57 22. NORMALIZE .....................................................................59 23. DERIVE EXPONENT........................................................61 24. BLOCK EXPINENT ADJUST...........................................64 25. ARITHMETIC SHIFT IMMEDIATE ................................65 26. LOGICAL SHIFT IMMEDIATE .......................................67 27. REGISTER MOVE ............................................................68 28. LOAD REGISTER IMMEDIATE......................................70 29. DATA MEMORY READ (Direct Address) ........................72 30. DATA MEMORY READ (Indirect Address) .....................73 31. PROGRAM MEMORY READ (Indirect Address) ............74 32. DATA MEMORY WRITE (Direct Address) ......................76 33. DATA MEMORY WRITE (Indirect Address) ....................77 34. PROGRAM MEMORY WRITE (Indirect Address) ..........79 35. I/O SPACE READ/WRITE ................................................80 36. JUMP ..................................................................................81 37. CALL ..................................................................................82

38. JUMP or CALL ON FLAG IN PIN....................................84 39. MODIFY FLAG OUT PIN.................................................85 40. RTS .....................................................................................86 41. RTI ......................................................................................87 42. DO UNTIL ..........................................................................88 43. IDLE ...................................................................................90 44. STACK CONTROL ............................................................92 45. TOPPCSTACK ...................................................................94 46. MODE CONTROL .............................................................96 47. MODIFY ADDRESS REGISTER .....................................98 48. NOP ....................................................................................99 49. INTERRUPT ENABLE & DISABLE ...............................99 50. COMPUTATION with MEMORY READ .......................100 51. COMPUTATION with REGISTER to REGISTER MOVE .........................................................................................................104 52. COMPUTATION with MEMORY WRITE .....................108 53. DATA & PROGRAM MEMORY READ......................... 111 54. ALU/MAC with DATA & PROGRAM MEMORY READ ......................................................................................................... 113 55. 附录 ................................................................................. 116 A. Table 15.1 ................................................................... 116 B. Table 15.2 ................................................................... 117

C. Table 15.3 ................................................................... 118 D. Table 15.4 ................................................................... 118 E. Table 15.5 ................................................................... 119 F. Table 15.6 .................................................................... 119 G. Table 15.7 ...................................................................120 H. Table 15.8 ...................................................................120 I. Table 15.9 ....................................................................121 J. Table 15.10 ..................................................................122

61IC 中国电子在线 DSP 汇编指令集

一、SUMMARIZE
1、QUICK LIST OF INSTRUCTIONS
This chapter is a complete reference for the instruction set of the ADSP-2100 family. The instruction set is organized by instruction group and, within each group, by individual instruction. The list below shows all of the instructions and the reference page for each. ALU: Add/Add with Carry Subtract X-Y/Subtract X-Y with Borrow Subtract Y-X/Subtract Y-X with Borrow AND, OR, XOR Test Bit, Set Bit, Clear Bit, Toggle Bit Pass/Clear Negate NOT Absolute Value Increment Decrement Divide Generate ALU Status MAC: Multiply
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Multiply/Accumulate Multiply/Subtract Clear Transfer MR Conditional MR saturation SHIFTER: Arithmetic Shift Logical Shift Normalize Derive Exponent Block Exponent Adjust Arithmetic Shift Immediate Logical Shift Immediate MOVE: Register Move Load Register Immediate Data Memory Read (Direct Address) Data Memory Read (Indirect Address) Program Memory Read (Direct Address) Program Memory Read (Indirect Address) Data Memory Write (Direct Address) Data Memory Write (Indirect Address)
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Program Memory Write (Indirect Address) I/O Space Read/Write PROGRAM FLOW: JUMP CALL JUMP or CALL on Flag In Pin Modify Flag Out Pin Return from Subroutine Return from Interrupt Do Until IDLE MISC: Stack Control Mode Control Modify Address Register NOP Interrupt Enable & Disable MULTIFUNCTION: ALU/MAC/SHIFT with Memory Read ALU/MAC/SHIFT with Data Register Move ALU/MAC/SHIFT with Memory Write Data & Program Memory Read
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ALU/MAC with Data & Program Memory Read

2、OVERVIEW
This chapter provides an overview and detailed reference for the instruction set of the ADSP-2100 family of DSP microprocessors. For information regarding the ADSP-2100 Family Development Software, refer to the ADSP-2100 Family Assembler Tools & Simulator Manual, ADSP-2100 Family C Tools Manual, and ADSP-2100 Family C Runtime Library Manual. These manuals provide a complete guide to the development software. The handbooks Digital Signal Processing Applications Using The ADSP-2100 Family, Volume 1 and Volume 2 present DSP applications programs with source code and discussion. The instruction set is tailored to the computation-intensive algorithms common in DSP applications. For example, sustained single-cycle multiplication/accumulation operations are possible. The instruction set provides full control of the processors ‘ three computational units: the ALU, MAC and Shifter. Arithmetic instructions can process single-precision 16-bit operands directly; provisions for multiprecision operations are available. The high-level syntax of ADSP-2100 family source code is both readable and efficient. Unlike many assembly languages, the ADSP-2100 family instruction set uses an algebraic notation for arithmetic operations and for data moves, resulting in highly readable source code. There is no
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performance penalty for this; each program statement assembles into one 24-bit instruction, which executes in a single cycle. There are no multicycle instructions in the instruction set. (If memory access times require, or contention for off-chip memory occurs, overhead cycles will be required, but all instructions can otherwise execute in a single cycle.) In addition to JUMP and CALL, the instruction set‘s control instructions support conditional execution of most calculations and a DO UNTIL looping instruction. Return from interrupt (RTI) and return from subroutine (RTS) are also provided. The IDLE instruction is provided for idling the processor until an interrupt occurs. IDLE puts the processor into a low-power state while waiting for interrupts. Two addressing modes are supported for memory fetches. Direct addressing uses immediate address values; indirect addressing uses the I registers of the two data address generators (DAGs). The 24-bit instruction word allows a high degree of parallelism in performing operations. The instruction set allows for single-cycle execution of any of the following combinations: any ALU, MAC or Shifter operation(conditional or non-conditional) any register-to-register move any data memory read or write a computation with any data register to data register move
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a computation with any memory read or write a computation with a read from two memories. The instruction set allows maximum flexibility. It provides moves from any register to any other register, and from most registers to/from memory. In addition, almost any ALU, MAC or Shifter operation may be combined with any register-to-register move or with a register move to or from either internal or external memory.

3、INTRUCTION TYPES & NOTATION CONVENTIONS
The ADSP-2100 family instruction set is grouped into following categories: Computational: ALU, AMC, Shifter Move Program Flow Multifunction Miscellaneous Because the multifunction instructions best illustrate the power of the processors‘ architecture, in the next section we begin with a discussion of this group of instructions. Throughout this chapter you will find tables summarizing the syntax of the instruction groups. The following notation conventions are used in these tables and in the reference page for each instruction. Square Brackets [] Anything within squareBrackets is an optional
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part Of the instruction statement. Parallel Lines | | Lists of operands are Enclosed by vertical

parallel Bars. One of the operands Listed must be chosen. If the Parallel bars are within Square brackets, then the Operand is optional for that Instruction. CAPITAL LETTERS Capital letters denote a literal in the instruction. Literals are the instruction name(e.g. ADD), register names, or Operand selections. Literals Must be typed exactly as shown. Operands Some instruction operands are Shown in lowercase

letters. These operands may take Different values in assembly Code. For example, the Operand yop may be one of Several registers; AY0, AY1, Or AF. <exp> Denotes exponent (shift value) in Shift Immediate

instructions; must be an 8-bit signed integer constant. <data> Denotes an immediate data value. Can also be a symbol

(address label or variable/buffer name) dereferenced by the ?%‘ or ?^‘operators. <addr> Denotes an immediate address value to be encoded in

the instruction. The <addr> may be either an immediate value (a constant) or a program label. <reg> <dreg> Refers to any accessible register. Refers to any data register.
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Immediate values, <exp>,<data>,or <addr>, may be a constant in decimal, hexadecimal, octal or binary format. Default is to decimal.

4、MULTIFUNCTION INSTRUCTIONS
Multifunction operations take advantage of the inherent parallelism of the ADSP-2100 family architecture by providing combinations of data moves, memory reads/memory writes, and computation, all in a single cycle. 4.1、ALU/MAC With Data & Program Memory Read Perhaps the single most common operation in DSP algorithms is the sum of products, performed as follows: Fetch two operands (such as a coefficient and data point) Multiply the operands and sum the result with previous products The ADSP-2100 family processors can execute both data fetches and the multiplication/accumulation in a single-cycle. Typically, a loop of multiply/accumulates can be expressed in ADSP-21** source code in just two program lines. Since the on-chip program memory of the ADSP-21** processors is fast enough to provide an operand and the next instruction in a single cycle, loops of this type can execute with sustained single-cycle throughput. An example of such an instruction is: MR=MR+MX0*MY0(SS),MX0=DM(I0,M0),\ MY0=PM(I4,M5); The first clause of this instruction (up to the first comma) says that
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MR, the MAC result register, gets the sum of its previous value plus the product of the (current) X and Y input registers of the MAC (MX0 and MY0) both treated as signed (SS). In the second and third clauses of this multifunction instruction two new operands are fetched. One is fetched from the data memory (DM) pointed to by index register zero (I0, post modified by the value in M0) and the other is fetched from the program memory location (PM) pointed to by I4 (post-modified by M5 in this instance). Note that indirect memory addressing uses a syntax similar to array indexing, with DAG registers providing the index values. Any I register may be paired with any M register within the same DAG. As discussed in Chapter 2, ―Computational Units‖, registers are read at the beginning of the cycle and written at the end of the cycle. The operands present in the MX0 and MY0 registers at the beginning of the instruction cycle are multiplied and added to the MAC result register, MR. The new operands fetched at the end of this same instruction overwrite the old operands after the multiplication has taken place and are available for computation on the following cycle. You may, of course, load any data registers in conjunction with the computation, not just MAC registers with a MAC operation as in our example. The computational part of this multifunction instruction may be any unconditional ALU instruction except division or any MAC instruction
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except saturation. Certain other restrictions apply: the next X operand must be loaded in MX0 from data memory and the new Y operand must be loaded into MY0 from program memory (internal and external memory are identical at the level of the instruction set). The result of the computation must go to the result register (MR or AR) not to the feedback register (MF or AF). 4.2、Data & Program Memory Read This variation of a multifunction instruction is a special case of the multifunction instruction described above in which the computation is omitted. It executes only the dual operand fetch, as shown below: AX0=DM(I2,M0), AY0=PM(I4,M6); In this example we have used the ALU input registers as the destination. As with the previous multifunction instruction, X operands must come from data memory and Y operands from program memory (internal or external memory in either case, for the processors with on-chip memory). 4.3、Computation With Memory Read If a single memory read is performed instead of the dual memory read of the previous two multifunction instructions, a wider range of computations can be executed. The legal computations include all ALU operations except division, all MAC operations and all Shifter operations except SHIFT IMMEDIATE. Computation must be unconditional. An
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example of this kind of multifunction instruction is: AR=AX0+AY0, AX0=DM(I0,M3); Here an addition is performed in the ALU while a single operand is fetched from data memory. The restrictions are similar to those for previous multifunction instructions. The value of AX0, used as a source for the computation, is the value at the beginning of the cycle. The data read operation loads a new value into AX0 by the end of the cycle. For this same reason, the destination register (AR in the example above) cannot be the destination for the memory read. 4.4、Computation With Memory Write The computation with memory write instruction is similar in structure to the computation with memory read: the order of the clauses in the instruction line, however, is reversed. First the memory write is performed, then eht computation, as shown below: DM(I0,M0)=AR, AR=AX0+AY0; Again the value of the source for the memory write (AR in this example) is the value at the beginning of the instruction. The computation loads a new value into the same register; this is the value in AR at the end of this instruction. Reversing the order of the clauses of the instruction is illegal and causes the assembler to generate a warning; in would imply that the result of the computation is written to memory when, in fact, the previous value of the register is what is written. There is no requirement
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that the same register be used in this way although this will usually be the case in order to pipeline operands to the computation. The restrictions on computation operations are identical to those given above. All ALU operations except division, all MAC operations, and all Shifter operations except SHIFT IMMEDIATE are legal. Computations must be unconditional. 4.5、Computation With Data Register Move This final type of multifunction instruction performs a data register to data register move in parallel with a computation. Most of the restrictions applying to the previous two instructions also apply to this instruction. AR=AX0+AY0, AX0=MR2; Here an ALU addition operation occurs while a new value is loaded into AX0 from MR2. As before, the value of AX0 at the beginning of the instruction is the value used in the computation. The move may be from or to all ALU, MAC and Shifter input and output registers except the feedback registers (AF and MF) and SB. In the example, the data register move loads the AX0 register with the new value at the end of the cycle. All ALU operations except division, all MAC operations and all Shifter operations except SHIFT IMMEDIATE are legal. Computation must be unconditional. A complete list of data registers is given in Table 15.7. A complete
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list of the permissible xops and yops for computational operations is giver in the combinations for multifunction instructions: you may combine operations on the same row with each other.

5、ALU, MAC & SHIFTER INSTRUCTION
This group of instructions performs computations. All of these instructions can be executed conditionally except the ALU division instruction and the Shifter SHIFT IMMEDIATE instruction. 5.1、ALU Group Here is an example of one ALU instruction, Add/Add with Carry: IF AC AR=AX0+AY0+C; The (optional) conditional expression, IF AC, tests the ALU Carry bit (AC);if there is a carry from the previous instruction, this instruction executes, otherwise a NOP occurs and execution continues with the next instruction. The algebraic expression AR=AX0+AY0+C means that the ALU result register (AR) gets the value of the ALU X input and Y input registers plus the value of the carry-in bit. Table 15.3 gives a summary list of all ALU instruction. In this list, condition stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the ALU. The conditional clause is optional and is enclosed in square brackets to show this. A complete list of the permissible xops and yops is given in the reference page for each instruction. A complete list of conditions is given
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in Table 15.9. 5.2、MAC Group Here is an example of one of the MAC instructions,

Multiply/Accumulate: IF NOT MV MR=MR+MX0*MY0(UU); The conditional expression, IF NOT MV, tests the MAC overflow bit. If the condition is not true, a NOP is executed. The expression MR=MR+MX0*MY0 is the multiply/accumulate operation: the

multiplier result register (MR) gets the value of itself plus the product of the X and Y input registers selected. The modifier in parentheses (UU) treats the operands as unsigned. There can be only one such modifier selected from the available set. (SS) means both are singed, while (US) and (SU) mean that either the first or second operand is signed; (RND) means to round the (implicitly signed) result. Table 15.4 gives a summary list of all MAC instructions. In this list, condition stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the MAC. A complete list of the permissible xops and yops is given in the reference page for each instruction. 5.3、Shifter Group Here is an example of one of the Shifter instructions, Normalize: IF NOT CE SR=SR OR NORM SI (HI);
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The conditional expression, IF NOT CE, tests the ―not counter expired‖ condition. If the condition is false, a NOP is executed. The destination of all shifting operations is the Shifter Result register, SR. (The destination of exponent detection instructions is SE or SB, as shown below.) In this example, SI, the Shifter Input register, is the operand. The amount and direction of the shift is controlled by the signed value in the SE register in all shift operations except an immediate shift. Positive values cause left shifts; negative values cause right shifts. The ―SR OR‖ modifier (which is optional) logically Ors the result with the current contents of the SR register; this allows you to construct a 32-bit value in SR from two 16-bit pieces. ―NORM‖ is the operator and ―(HI)‖is the modifier that determines whether the shift is relative to the HI or LO (16-bit) half of SR. If ―SR OR‖ is omitted, the result is passed directly into SR. Table 15.5 gives a summary list of all Shifter instructions. In this list, condition stands for all the possible conditions that can be tested.

6、MOVE: READ & WRITE
MOVE instructions, shows in table 15.6, move data to and from data registers and external memory. Registers are divided into two groups, referred to as reg which includes almost all registers and dreg, or data registers, which is a subset. Only the program counter (PC) and the ALU and MAC feedback registers (AF and MF) are not accessible.
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Table 15.7 shows which registers belong to these groups. Many of the system control registers are memory -mapped (for the processors with on-chip memory); these registers are read and written as memory locations instead of with register names.

7、PROGRAM FLOW CONTROL
Program flow control on the ADSP-2100 family processors is simple but powerful. Here is an example of one instruction: IF EQ JUMP my_label; JUMP, of course, is a familiar construct from many other languages. My_label is any identifier you wish to use as a label for the destination jumped to. Instead of the label, an index register in DAG2 may be explicitly used. The default scope for any label is the source code module in which it is declared. The assembler directive .ENTRY makes a label visible as an entry point for routines outside the module. Conversely, the .EXTERNAL directive makes it possible to use a label declared in another module. If the counter condition (CE, NOT CE) is to be used, an assignment to CNTR must be executed to initialize the counter value, JUMP and CALL permit the additional conditionals ―FLAG_IN‖ and ―NOT FLAG_IN‖ to be used for branching on the state of the FI pin, but only with direct addressing, not with DAG2 as the address source. RTS (return from subroutine) and RTI (return from interrupt)
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provide for conditional return from CALL or interrupt vectors respectively. The IDLE instruction provides a way to wait for interrupts. IDLE causes the processor to wait in a low-power state until an interrupt occurs. When an interrupt is serviced, control returns to the instruction following the IDLE statement. IDLE uses less power than loops created with JUMP. Table 15.8 gives a summary of all program flow control instructions. The condition codes are described in table 15.9.

8、MISCELLANEOUS INSTRUCTIONS
There are several miscellaneous instructions. NOP is a no operation instruction. The PUSH/POP instructions allows you to explicitly control the status, counter, PC and loop stacks; interrupt servicing automatically pushes and pops some of these stacks. The Mode Control instruction enables and disables processor modes of operation: bit-reversal on DAG1, latching ALU overflow, saturating the ALU result register, choosing the primary or secondary register set, GO mode for continued operation during bus grant, multiplier shift mode for fractional or integer arithmetic, and timer enabling. A single ENA or DIS can be followed by any number of mode identifiers, separated by commas; ENA and DIS can also be repeated. All seven modes can be enabled, disabled, or changed in a single instruction. The MODIFY instruction modifies the address pointer in the I
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register selected with the value in the selected M register, without performing any actual memory access. As always, the I and M registers must be from the same DAG; any of I0-I3 may be used only with one from MO-M3 and the same for I4-I7 and M4-M7. If circular buffering is in use, modulus logic applies (See Chapter 4, ―Data Transfer‖, for more information). The FO (Flag Out), FL0, FL1 and FL2 pins can each be set, cleared, or toggled. This instruction provides a control structure for

multiprocessor communication.

9、EXTRA CYCLE CONDITIONS
All instructions execute in a single cycle except under certain conditions, as explained below. 9.1、Multiple Off-Chip Memory Accesses The data and address busses of the ADSP-21** processors are multiplexed off-chip. Because of this, the processors can perform only one off-chip access per instruction in a single cycle. If two off-chip accesses are required — the instruction fetch and one data fetch, for example, or data fetches from both program and data memory — then one overhead cycle occurs. In this case the program memory access occurs first, then the data memory access. If three off-chip accesses are required — the instruction fetch as well as data fetches from both program and memory — then two overhead cycles occur.
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A multifunction instruction requires three items to be fetched from memory: the instruction itself and two data words. No extra cycle is needed to execute the instruction as long as only one of the fetches is from external memory. (Two fetches must be from on-chip memory, either PM or DM.) 9.2、Wait States All family processors allow the programming of wait states for external memory chips. Up to seven extra wait state cycles may be added to the processor ‘s access time for external memory. Extra cycles inserted due to wait states are in addition to any caused by multiple off-chip accesses (as described above). Wait state programming is described in the ―Memory Interface‖ chapter. Wait states and multiple off-chip memory accesses are the two cases when an extra cycle is generated during instruction execution. The following case, SPORT autobuffering and DMA, causes the insertion of extra cycles between instructions. 9.3、SPORT Autobuffering & DMA If serial port autobuffing or ADSP-2181 DMA is being used to transfer data words to or from internal memory, then one memory access is ―stolen‖ for each transfer. The stolen memory access occurs only between complete instructions. If extra cycles are required to execute any instruction (for one of the two reasons above), the processor waits until it
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is completed before ―stealing‖ the access cycle.

10、INSTRUCTION SET SYNTAX
The following sections describe instruction set syntax and other notation conventions used in the reference page of each instruction. 10.1、Punctuation & Multifunction Instructions All instructions terminate with a semicolon. A comma separates the clauses of a multifunction instruction but does not terminate it. For example, the statements below in Example A comprise one multifunction instruction (which can execute in a single cycle). Example B shows two separate instructions, requiring two instruction cycles. Example A: one multifunction instruction AX0=DM(I0,M0), a comma is used in multifunction instructions AY0=PM(I4,M4); Example B: Two separate instructions AX0=DM(I0,M0); a semicolon terminates an instruction AY0=PM(I4,M4); 10.2、Syntax Notation Example Here is an example of one instruction, the ALU Add/Add with Carry instruction:
[IF cond] AR AF ? xop ? yop C yop ? C ;

The permissible conds, xops and yops are given in a list. The conditional IF clause is enclosed in square brackets, indicating that it is
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optional. The destination register for the add operation must be either AR or AF. These are listed within parallel bars, indicating that one of the two must be chosen. Similarly, the yop term may consist of a Y operand, the carry bit, or the sum of both. One of these three terms must be used. 10.3、Status Register Notation The following notation is used in the discussion of the effect each instruction has on the processors‘ status register: * An asterisk indicates a bit in the status word that is changed by the execution of the instruction. - A dash indicates that a bit is not affected by the instruction. 0 or 1 Indicates that a bit is unconditionally cleared or set.

For example, the status word ASTAT is shown below: A STAT: S 7 S V 6 M Q * 5 A S 4 A C 3 A V 2 A N 0 1 A Z 0 A

here the MV bit is updated and the AV bit is cleared.

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二、DSP INSTRUCTIONS
1. ADD/ADD with CARRY
[IF cond] | AR | ? xop | ? yop | | | | ; | AF | | ?C | ? yop ? C | ?cons tan t

Syntax:
Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

| ?cons tan t ? C |

Permissible yops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Permissible constants (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 0,1,2,4,8,16,32,64,128,256,1024,2048,4096,8192,16384,32767 -2,-3,-5,-9,-17,-33,-65,-129,-257,-513,-1025,-2049,-4097,-8193,-16385,-32768

Example: IF EQ AR=AX0+AY0+C; AR=AR+512; Description: Test the optional condition and, if true, perform the specified addition. If false then perform a no-operation. Omitting the condition performs the addition unconditionally. The addition operation adds the first source operand to the second source operand along with the ALU carry bit, AC, (if designated by the ―+C‖ notation), using binary addition. The result is stored in the destination register. The operands are contained in the data register or constant specified in the instruction. The xop + constant operation is only available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors and may not be used in

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multifunction instructions. Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V * 2 A N * 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set if an arithmetic overflow occurs. Cleared otherwise. AC set if a carry is generated. Cleared otherwise.

Instruction Format:
Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF=10010 for xop + yop + C AMF=10011 for xop + yop (Note that xop + C is a special case of xop + yop + C with yop=0.) Z: Destination register Xop: X operand Yop: Y operand COND: condition

(xop+constant) Conditional ALU/MAC operation, Instruction Type 9: (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND

AMF=10010 for xop + constant + C AMF=10011 for xop + constant Z: Destination register Xop: X operand COND: condition

第 23 页

61IC 中国电子在线 DSP 汇编指令集 BO, CC,and YY specify the constant.

2. SUBTRACT X-Y/SUBTRACT X-Y with BORROW
[IF cond] | AR | ? xop | ? yop | | | | ;

Syntax:
Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

| AF |

| ? yop? C ? 1 | ?C ? 1 | ?cons tan t

| ?cons tan t ? C ? 1 |

Permissible yops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Permissible constants (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 0,1,2,4,8,16,32,64,128,256,1024,2048,4096,8192,16384,32767 -2,-3,-5,-9,-17,-33,-65,-129,-257,-513,-1025,-2049,-4097,-8193,-16385,-32768

Example: IF GE AR=AX0-AY0; Description: Test the optional condition and, if true, then perform the specified subtraction. If the condition is not true then perform a no-operation. Omitting the condition perform the subtraction

unconditionally. The subtraction operation subtracts the second source operand from the first source operand, and optionally adds the ALU Carry bit (AC) minus 1 (H#0001), and stores the result in the destination register. The (C-1) quantity effectively implements a borrow capability for multiprecision subtractions. The operands are contained in the data registers or constant specified in the instruction. The xop-constant operation is only available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors and may not be used in
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61IC 中国电子在线 DSP 汇编指令集

multifunction instructions. Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V * 2 A N * 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set if an arithmetic overflow occurs. Cleared otherwise. AC set if a carry is generated. Cleared otherwise. Instruction Format: Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF=10110 for xop - yop + C-1 operation. AMF=10111 for xop – yop operation. (Note that xop + C – 1 is a special case of xop - yop + C - 1 with yop=0.) Z: Destination register Xop: X operand Yop: Y operand COND: condition

(xop+constant) Conditional ALU/MAC operation, Instruction Type 9: (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND

AMF=10110 for xop - constant + C - 1 AMF=10111 for xop - constant Z: Destination register Xop: X operand BO, CC,and YY specify the constant.
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COND: condition

61IC 中国电子在线 DSP 汇编指令集

3. SUBTRACT Y-X/ SUBTRACT Y-X with BORROW
[IF cond] | AR | ? | yop ? | xop | | ; | | |

Syntax:
Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

| AF |

| | | |

? | xop ? C ? 1 | ? xop ? C ? 1 ? xop ? cons tan t

? xop ? cons tan t ? C ? 1 |

Permissible yops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Permissible constants (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 0,1,2,4,8,16,32,64,128,256,1024,2048,4096,8192,16384,32767 -2,-3,-5,-9,-17,-33,-65,-129,-257,-513,-1025,-2049,-4097,-8193,-16385,-32768

Example: IF GT AR=AY0-AX0+C-1; Description: Test the optional condition and, if true, then perform the specified subtraction. If the condition is not true then perform a no-operation. Omitting the condition performs the subtraction

unconditionally. The subtraction operation subtracts the second source operand from the first source operand, optionally adds the ALU Carry bit (AC) minus 1 (H#0001), and stores the result in the destination register. The (C-1) quantity effectively implements a borrow capability for mulitipercision subtractions. The operands are contained in the data registers or constant specified in the instruction. The –xop+constant operation is only available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors and may not be used in

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61IC 中国电子在线 DSP 汇编指令集

multifunction instructions. Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V * 2 A N * 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set if an arithmetic overflow occurs. Cleared otherwise. AC set if a carry is generated. Cleared otherwise.

Instruction Format:
Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF=11010 for yop - xop + C-1 AMF=11001 for yop – xop (Note that - xop + C - 1 is a special case of yop - xop + C - 1 with yop=0.) Z: Destination register Xop: X operand Yop: Y operand COND: condition

(-xop+constant) Conditional ALU/MAC operation, Instruction Type 9: (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND

AMF=11010 for constant - xop + C - 1 AMF=10111 for constant - xop Z: Destination register Xop: X operand COND: condition

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61IC 中国电子在线 DSP 汇编指令集 BO, CC,and YY specify the constant.

4. AND, OR, XOR
Syntax:
[IF cond] AR AF AND ? xop OR XOR yop ; cons tan t

Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

Permissible yops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Permissible constants (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 0,1,2,4,8,16,32,64,128,256,1024,2048,4096,8192,16384,32767 -2,-3,-5,-9,-17,-33,-65,-129,-257,-513,-1025,-2049,-4097,-8193,-16385,-32768

Example: AR=AX0 XOR AY0; IF FLAG_IN AR=MR0 AND 8192; Description: Test the optional condition and, if true, then perform the specified bitwise logical operation (logical AND, inclusive OR, or exclusive OR). If the condition is not true then perform a no-operation. Omitting the condition performs the logical operation unconditionally. The operands are contained in the data registers or constant specified in the instruction. The xop AND/OR/XOR constant operation is only available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors and may not be used in multifunction instructions. Status Generated:
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61IC 中国电子在线 DSP 汇编指令集 A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V 0 2 A N 0 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set Always Cleared. AC set Always Cleared.

Instruction Format:
Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF=11100 for AND operation AMF=11101 for OR operation AMF=11110 for XOR operation Z: Destination register Xop: X operand Yop: Y operand COND: condition

(xop AND/OR/XOR constant) Conditional ALU/MAC operation, Instruction Type 9: (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND

AMF=11100 for AND operation AMF=11101 for OR operation AMF=11110 for XOR operation Z: Destination register Xop: X operand BO, CC,and YY specify the constant. COND: condition

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61IC 中国电子在线 DSP 汇编指令集

5. TEST BIT,SET BIT,CLEAR BIT, TOGGLE BIT
(ADSP-217x,ADSP-218x, ADSP-21msp58/59 only)
TSTBIT n OF xop SETBIT n OF xop ; CLRBIT n OF xop TGLBIT n OF xop

Synatx:

[IF cond]

AR AF

?

Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 Permissible n values (0=LSB) MR0

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15

Example: AF=TSTBIT 5 OF AR; AR=TGLBIT 13 OF AX0; Description: Test the optional condition and if true, then perform the specified bit operation. If the condition is not true then perform a no-operation. Omitting the condition performs the operation

unconditionally. These operations cannot be used in multifunction instruction. These operation are defined as follows: TSTBIT is an AND operation with a 1 in the selected bit SETBIT is an OR operation with a 1 in the selected bit CLRBIT is an AND operation with a 0 in the selected bit TGLBIT is an XOR operation with a 1 in the selected bit The ASTAT status bits are affected by these instructions. The
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61IC 中国电子在线 DSP 汇编指令集

following instructions could be used, for example, to test a bit and branch accordingly: AF=TSTBIT 5 OF AR; IF NE JUMP set; /* Jump to ―set‖ if bit 5 of AR is set*/ Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V 0 2 A N 0 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set Always Cleared. AC set Always Cleared.

Instruction Format:
(xop AND/OR/XOR constant) Conditional ALU/MAC operation, Instruction type 9: (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND

AMF=11100 for AND operation AMF=11101 for OR operation AMF=11110 for XOR operation Z: Destination register Xop: X operand BO, CC,and YY specify the constant. COND: condition

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61IC 中国电子在线 DSP 汇编指令集

6. PASS/CLEAR
Syntax:
[IF cond] AR AF ? PASS xop yop ; constan t

Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

Permissible yops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Permissible constants (all ADSP-21xx processors) -1,0,1 Permissible constants (ADSP-217x,ADSP-218x,ADSP-21msp58/59 only) 2,3,4,5,7,8,9,15,16,17,31,32,33,63,64,65,127,128,129,255,256,257,511,512,513,1023,1024,1 025,2047,2048,2049,4095,4096,4097,8191,8192,8193,16383,16384,16385,32766,32767 -2,-3,-4,-5,-6,-8,-9,-10,-16,-17,-18,-32,-33,-34,-64,-65,-66,-128,-129,-130,-256-257,-258,-512 ,-513,-514,-1024,-1025,-1026,-16384,-16385,-16386,-32767,-32768

Examples: IF GE AR = PASS AY0; AR = PASS 0; AR = PASS 8191;
(ADSP-217x,ADSP-218x,ADSP-21msp58/59 only)

Description: Test the optional condition and if true, pass the source operand unmodified through the ALU block and store in the destination register. If the condition is not true perform a no-operation. Omitting the condition performs the PASS unconditionally. The source operand is contained in the data register or constant specified in the instruction. PASS 0 is one method of clearing AR. PASS 0 can also be combined
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61IC 中国电子在线 DSP 汇编指令集

with memory reads and writes in multifunction instruction to clear AR. The PASS instruction performs the transfer to the AR or AF register and affects the ASTAT status flags (for xop, yop, -1, 0, 1 only). This instruction is different from a register move operation which does not affect any status flags. The PASS constant operation (using any constant other than –1,0, or 1) causes the ASTAT status flags to be undefined. The PASS constant operation (using any constant other than –1,0, or 1) is only available on the ADSP-217x, ADSP-218x, and

ADSP-21msp58/59 processors and may not be used in multifunction instructions. Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V 0 2 A N 0 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set Always Cleared. AC set Always Cleared. Note: The PASS constant operation (using any constant other than –1,0,or 1) causes the ASTAT status flags to be undefined.

Instruction Format:
Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case:
第 33 页

61IC 中国电子在线 DSP 汇编指令集 AMF=10000 for PASS yop AMF=10011 for PASS xop AMF=10001 for PASS 1 AMF=11001 for PASS –1 Note that PASS xop is a special case of xop+yop, with yop=0. Note that PASS 1 is a special case of yop+1, with yop=0. Note that PASS –1 is a special case of yop-1, with yop=0. Z: Destination register Xop: X operand Yop: Y operand COND: condition

Conditional ALU/MAC operation, Instruction type 9: (PASS constant; constant ≠0,1,-1) (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND

AMF specifies the ALU or MAC operation. In this case, AMF=10000 for PASS yop (special case of yop, with yop=constant)

AMF=10001 for PASS yop+1 (special case of yop+1, with yop=constant) AMF=11000 for PASS yop-1 Z: Destination register Xop: X operand BO, CC,and YY specify the constant. (special case of yop-1, with yop=constant)

COND: condition

7. NEGATE
Syntax:
[IF cond] AR AF ? ? xop ; yop

Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

Permissible yops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

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61IC 中国电子在线 DSP 汇编指令集

Examples: IF LT AR = - AY0; Description: Test the optional condition and if true, then NEGATE the source operand and store in the destination location. If the condition is not true then perform a no-operation. Omitting the condition performs the NEGATE operation unconditionally. The source operand is contained in the data register specified in the instruction. Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V * 2 A N * 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set if operation=H#8000. Cleared otherwise. AC set if operation equals zero. Cleared otherwise.

Instruction Format:
Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF=10101 for –yop operation. AMF=11001 for –xop operation. Note that -xop is a special case of yop-xop, with yop specified to 0. Z: Destination register Xop: X operand Yop: Y operand COND: condition

第 35 页

61IC 中国电子在线 DSP 汇编指令集

8. NOT
Syntax:
[IF cond] AR AF ? NOT xop ; yop

Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

Permissible yops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Examples: IF NE AR = NOT AY0; Description: Test the optional condition and if true, then perform the logical complement (ones complement) of the source operand and store in the destination location. If the condition is not true then perform a no-operation. Omitting the condition performs the complement operation unconditionally. The source operand is contained in the data register specified in the instruction. Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V 0 2 A N 0 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV Always Cleared. AC Always Cleared.

Instruction Format:
Conditional ALU/MAC operation, Instruction Type 9:
第 36 页

61IC 中国电子在线 DSP 汇编指令集 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF=10100 for NOT yop operation. AMF=11011 for NOT xop operation. Z: Destination register Xop: X operand Yop: Y operand COND: condition

9. ABSOLUTE VALUE
Syntax:
[IF cond] AR AF ? ABS xop ;

Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Examples: IF NEG AF = ABS AX0; Description: Test the optional condition and, if true, then perform the absolute value of the source operand and store in the destination location. If the condition is not true then perform a no-operation. Omitting the condition performs the absolute value operation

unconditionally. The source operand is contained in the data register specified in the instruction. Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

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61IC 中国电子在线 DSP 汇编指令集 * 0 * * *

AZ set if the result equals zero. Cleared otherwise. AN set if xop is H#8000. Cleared otherwise.

AV set if xop is H#8000. Cleared otherwise. AC Always Cleared. AS set if the source operand is negative. Clear otherwise.

Instruction Format:
Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 0 0 Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF=11111 for ABS xop operation. Z: Destination register Xop: X operand COND: condition

10. INCREMENT
Syntax:
[IF cond] AR AF ? yop ? 1 ;

Permissible xops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Examples: IF GT AF = AF + 1; Description: Test the optional condition and, if true, then increment the source operand by H#0001 and store in the destination location. If the condition is not true then perform a no-operation. Omitting the condition performs the increment operation unconditi -onally. The source operand
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61IC 中国电子在线 DSP 汇编指令集

is contained in the data register specified in the instruction. Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V * 2 A N * 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set if an overflow is generated. Cleared otherwise. AC set if a carry is generated. Cleared otherwise.

Instruction Format:
Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF=10001 for yop+1 operation. Z: Destination register Xop: X operand Yop: Y operand COND: condition

11. DECREMENT
Syntax:
[IF cond] AR AF ? yop ? 1 ;

Permissible xops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Examples: IF EQ AR = AY1 - 1;

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61IC 中国电子在线 DSP 汇编指令集

Description: Test the optional condition and, if true, then decrement the source operand by H#0001 and store in the destination location. If the condition is not true then perform a no-operation. Omitting the condition performs the decrement operation unconditi -onally. The source operand is contained in the data register specified in the instruction. Status Generated:
A STAT: S 7 S V 6 M Q 5 A S 4 A C 3 A V * 2 A N * 1 A Z * * 0 A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set if an overflow is generated. Cleared otherwise. AC set if a carry is generated. Cleared otherwise.

Instruction Format:
Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF=11000 for yop-1 operation. Z: Destination register Xop: X operand Yop: Y operand COND: condition

12. DIVIDE
Syntax:
DIVS yop , xop ; DIVQ xop ;

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61IC 中国电子在线 DSP 汇编指令集 Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0 Permissible conds AY1 AF

Description: These instructions implement yop÷xop. There are two divide primitives, DIVS and DIVQ. A single precision divide, with a 32-bit numerator and a 16-bit denominator, yielding a 16-bit quotient, executes in 16 cycles. Higher precision divides are also possible. The division can be either signed or unsigned, but both the numerator and denominator must be the same; both signed or unsigned. The programmer sets up the divide by sorting the upper half of the numerator in any permissible yop (AY1 or AF), the lower half of the numerator in AY0,and the denominator in any permissible xop. The divide operation is then executed with the divide primitives,DIVS and DIVQ. Repeated execution of DIVQ implements a non-restoring conditional add-subtract division algorithm. At the conclusion of the divide operation the quotient will be in AY0. To implement a signed divide, first execute the DIVS instruction once, which computes the sign of the quotient. Then execute the DIVQ instruction for as many times as there are bits remaining in the quotient (e.g., for a signed, single-precision divide, execute DIVS once and DIVQ 15 times).
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61IC 中国电子在线 DSP 汇编指令集

To implement an unsigned divide, first place the upper half of the numerator in AF, then set the AQ bit to zero by manually clearing it in the Arithmetic Status Register, ASTAT. This indicates that the sign of the quotients is positive. Then execute the DIVQ instruction for as many times as there are bits in the quotient (e.g., for an unsigned single-precision divide, execute DIVQ 16 times). The quotient bit generated on each execution of DIVS and DIVQ is the AQ bit which is written to the ASTAT register at the end of each cycle. The final remainder produced by this algorithm (and left over in the AF register) is not valid and must be corrected if it is needed. For more information, consult the Division Exceptions appendix of this mannul. Status Generated:
A STAT: S 7 S V AQ 6 M Q 5 A S * 4 A C 3 A V 2 A N 1 A Z 0 A

Loaded with the bit value equal to the AQ bit computed on each cycle from execution

of the DIVS or DIVQ instruction.

Instruction Format:
DIVQ, Instruction Type 23: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 Xop 0 0 0 0 0 0 0 0 DIVS, Instruction Type 24: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 011 1 00 0 Yop Xop 0 0 0 0 0 0 0 0

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61IC 中国电子在线 DSP 汇编指令集 Xop: X operand Yop: Y operand

13. GENERATE ALU STATUS
(ADSP-217x, ADSP-218x, ADSP-21msp58/59 only)

Syntax:

NONE ? ? ALU ? ;

<ALU> may be any unconditional ALU operation except DIVS or DIVQ.*

Examples: NONE = AX0 – AY0; NONE = PASS SR0; Description: Perform the designated ALU operation, generate the ASTAT status flags, then discard the result value. This instruction allows the testing of register values with out disturbing the contents of the AR or AF registers. *Note that the additional-constant ALU operations of the ADSP-217x, ADSP-218x, ADSP-21msp58/59 processors are also not allowed: ADD (xop + constant) SUBTRACT X-Y (xop - constant) SUBTRACT Y-X (-xop+constant) AND, OR, XOR (xop×constant) PASS (PASS constant, using any constant other than –1, 0, or 1) TSTBIT, SETBIT, CLRBIT, TGLBIT. Status Generated:
A 7 6 5 4 3 2 1 0

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61IC 中国电子在线 DSP 汇编指令集 STAT: S S V M Q A S A C A V * A N * A Z * * A

AZ set if the result equals zero. Cleared otherwise. AN set if the result is negative. Cleared otherwise.

AV set if an overflow is generated. Cleared otherwise. AC set if a carry is generated. Cleared otherwise.

Instruction Format:
ALU/MAC operation with Data Register Move, Instruction Type 8: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 10101010

ALU codes only AMF specifies the ALU or MAC operation (only ALU operations are allowed). Xop: X operand Yop: Y operand

14. MULTIPLY
Syntax:
[IF cond] MR MF (SS) (SU ) xop ? xop ? ( US) ; yop ( UU ) (RND)

Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

Permissible yops AY0 AY1 AF

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Examples: IF EQ MR= MX0*MF(UU); {xop*yop} MF=SR0*SR0(SS); {xop*xop}

Description: Test the optional condition and if true, then multiply the two sources operand and store in the destination location. If the
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condition is not true then perform a no-operation. Omitting the condition performs the multiplication unconditionally. The operands are contained in the data register specified in the instruction. When MF is the destination operand, only bits 31-16 of the product are stored in MF. The xop*xop squaring operation is only available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors. Both xops must be the same register. This option allows single-cycle X2 and Σ X2 instructions. The data format selection field following the two operands specifies whether each respective operand is in Signed (S) or Unsigned (U) format. The xop is specified first and yop is second. If the xop*xop operation is used, the data format selection field must be (UU), (SS), or (RND) only. There is no default; one of the data formats must be specified. If RND (Round) is specified, the MAC multiplies the two source operands, rounds the result to the most significant 24 bits (or rounds bits 31-16 to 16 bits if there is no overflow from the multiply), and stores the result in the destination register. The two multiplication operands xop and yop (or xop and xop) are considered to be in twos complement format. All rounding is processors, which offer a biased rounding mode. For a discussion of biased vs. unbiased rounding, see ―Rounding Mode‖ in the ―Multiplier/ Accumulator‖ section of Chapter2, Computation Units. Status Generated:
A 7 6 5 4 3 2 1 0

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61IC 中国电子在线 DSP 汇编指令集 STAT: S S V * M Q A S A C A V A N A Z A

MV Set on MAC overflow (if any of upper 9 bits of MR are not all one or zero). Cleared otherwise.

Instruction Format:
(xop*yop) Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF 00100 00101 00110 00111 00001 FUNCTION Xop * yop Xop * yop Xop * yop Xop * yop Xop * yop Data Format (SS) (SU) (US) (UU) (RND) Yop: Y operand register COND: condition X-Operand Signed Signed Unsigned Unsigned Signed Y-Operand Signed Unsigned Signed Unsigned Signed

Z: Destination register Xop: X operand register

(xop*yop) Conditional ALU/MAC operation, Instruction Type 9: (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 00 Xop 0 0 0 1 COND

AMF specifies the ALU or MAC operation, in this case: AMF 00100 00111 00001 FUNCTION Xop * xop Xop * xop Xop * xop Data Format (SS) (UU) (RND) COND: condition X-Operand Signed Unsigned Signed

Z: Destination register Xop: X operand register

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15. MULTIPLY/ACCUMULATE
Syntax:
[IF cond] MR MF ? (SS) (SU) xop MR ? xop ? ( US) ; yop ( UU ) (RND)

Permissible xops AX0 MR2 AX1 MR1 AR SR1 SR0 MR0

Permissible yops AY0 AY1 AF

Permissible conds EQ NE GT GE LT CE LE AC

NEG NOT AC POS AV MV NOT MV NOT

NOT AV

Examples: IF GE MR=MR+MX0*MY1(SS); {xop*yop} MR=MR+MX0*MX0(SS); {xop*xop}

Description: Test the optional condition and, if true, then multiply the two source operands, add the product to the present contents of the MR register, and store the result in the destination location. If the conditions is not true then perform a no-operation. Omitting the condition perform the multiply/accumulate unconditionally. The operands are contained in the data registers specified in the instruction. When MF is the destination operand, only bits 31-16 of the 40-bits result are stored in MF. The xop*xop squaring operation is only available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors. Both xops must be the same register. This option allows single-cycle X2 and Σ X2 instructions. The data format selection field to the right of the two operands
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specifies whether each respective operand is in signed (S) or unsigned (U) format. The xop is specified first and yop is second. If the xop*xop operation is used, the data format selection field must be (UU), (SS) or (RND) only. There is no default; one of the data formats must be specified. If RND (Round) is specified, the MAC multiplies the two source operands, adds the product to the current contents of the MR register, rounds the result to the must significant 24 bits (or rounds bits 31-16 to the nearest 16 bits if there is no overflow from the multiply/accumulate), and stores the result in the destination register. The two multiplication operands xop and yop (or xop and xop) are considered to be in twos complement format. All rounding is unbiased, except on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors, which offer a biased rounding mode. For a discussion of biased vs. unbiased rounding, see ― Rounding Mode‖ in the ―Multiplier/ Accumulator‖ section of Chapter 2, Computation Units. Status Generated:
A STAT: S 7 S V * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

MV Set on MAC overflow (if any of upper 9 bits of MR are not all one or zero). Cleared otherwise.

Instruction Format:
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61IC 中国电子在线 DSP 汇编指令集 (xop*yop) Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF 01000 01001 01010 01011 000 10 yop Z: Destination register Xop: X operand register Yop: Y operand register COND: condition FUNCTION MR+xop * yop MR+xop * yop MR+xop * yop MR+xop * yop MR+xop * Data Format (SS) (SU) (US) (UU) (RND) X-Operand Signed Signed Unsigned Unsigned Signed Y-Operand Signed Unsigned Signed Unsigned Signed

(xop*yop) Conditional ALU/MAC operation, Instruction Type 9: (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 00 Xop 0 0 0 1 COND

AMF specifies the ALU or MAC operation, in this case: AMF 00100 00111 00001 FUNCTION MR+xop * xop MR+xop * xop MR+xop * xop Data Format (SS) (UU) (RND) X-Operand Signed Unsigned Signed

Z: Destination register Xop: X operand register

COND: condition

16. MULTIPLY/SUBTRACT
Syntax:
[IF cond] MR MF (SS) (SU) ? MR ? xop ? xop ( US) ; yop ( UU ) (RND)

Permissible xops

Permissible yops

Permissible conds

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61IC 中国电子在线 DSP 汇编指令集 AX0 MR2 AX1 MR1 AR SR1 SR0 MR0 AY0 AY1 AF EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Examples: IF LT MR=MR-MX0*MY0(SU); {xop*yop} MR=MR-MX0*MX0(SS); {xop*xop}

Description: Test the optional condition and, if true, then multiply the two source operands, subtract the product to the present contents of the MR register, and store the result in the destination location. If the condition is not true perform a no-operation. Omitting the condition performs the multiply/subtract unconditionally. The operands are contained in the data registers specified in the instruction. When MF is the destination operand, only bits 31-16 of the 40-bits result are stored in MF. The xop*xop squaring operation is only available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors. Both xops must be the same register. The data format selection field to the right of the two operands specifies whether each respective operand is in signed (S) or unsigned (U) format. The xop is specified first and yop is second. If the xop*xop operation is used, the data format selection field must be (UU), (SS) or (RND) only. There is no default; one of the data formats must be

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specified. If RND (Round) is specified, the MAC multiplies the two source operands, subtracts the product to the current contents of the MR register, rounds the result to the must significant 24 bits (or rounds bits 31-16 to 16 bits if there is no overflow from the multiply/accumulate), and stores the result in the destination register. The two multiplication operands xop and yop (or xop and xop) are considered to be in twos complement format. All rounding is unbiased, except on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors, which offer a biased rounding mode. For a discussion of biased vs. unbiased rounding, see ― Rounding Mode‖ in the ―Multiplier/ Accumulator‖ section of Chapter 2, Computation Units. Status Generated:
A STAT: S 7 S V * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

MV Set on MAC overflow (if any of upper 9 bits of MR are not all one or zero). Cleared otherwise.

Instruction Format:
(xop*yop) Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND

AMF specifies the ALU or MAC operation, in this case: AMF FUNCTION Data Format
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X-Operand

Y-Operand

61IC 中国电子在线 DSP 汇编指令集 01100 01101 01110 01111 00011 MR-xop * yop MR-xop * yop MR-xop * yop MR-xop * yop MR-xop * yop (SS) (SU) (US) (UU) (RND) Signed Signed Unsigned Unsigned Signed Signed Unsigned Signed Unsigned Signed

Z: Destination register Xop: X operand register

Yop: Y operand register COND: condition

(xop*yop) Conditional ALU/MAC operation, Instruction Type 9: (ADSP-217x,ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 00 Xop 0 0 0 1 COND

AMF specifies the ALU or MAC operation, in this case: AMF 01100 01111 00011 FUNCTION MR-xop * xop MR-xop * xop MR-xop * xop Data Format (SS) (UU) (RND) X-Operand Signed Unsigned Signed

Z: Destination register Xop: X operand register

COND: condition

17. CLEAR
Syntax:
[IF cond] MR MF ? 0 ;

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Examples: IF GT MR = 0; Description: Test the optional condition and, if true, then set the
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specified register to zero. If the condition is not true perform a no-operation. Omitting the condition performs the clear unconditionally. The entire 40-bit MR or 16-bit MF register is cleared to zero. Status Generated:
A STAT: S 7 S V MV 0 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

Always cleared.

Instruction Format:
ALU/MAC operation with Data Register Move, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 11 000 10101010

AMF: specifies the ALU or MAC operation .In this case, AMF=00100 for clear operation. Note that this instruction is a special case of xop*yop, with yop set to zero. Z: Destination register COND: condition.

18. TRANSFER MR
Syntax:
[IF cond] MR MF ? MR [( RND)] ;

Permissible conds EQ NE GT GE LT LE AC

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Examples: IF EQ MF = MR(RND); Description: Test the optional condition and, if true, then perform
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the MR transfer according to the description below. If the condition is not true then perform a no-operation. Omitting the condition performs the transfer unconditionally. This instruction actually performs a multiply/ accumulate, specifying yop=0 as a multiplicand and adding the zero product to the contents of MR. The MR register may be optionally rounded at the boundary between bits 15 and 16 of the result by specifying the RND option. If MF is specified as the destination, bits 31-16 of the result are stored in MF. If MR is the destination, the entire 40-bit result is stored in MR. Status Generated:
A STAT: S 7 S V MV otherwise. * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

Set on MAC overflow ( if any of upper 0 bits of MR are not all one or zero). Cleared

Instruction Format:
ALU/MAC operation with Data Register Move, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 11 0 0 0 1 0 1 0 COND

AMF: specifies the ALU or MAC operation .In this case, AMF=01000 for Transfer MR operation. Note that this instruction is a special case of MR + xop*yop, with yop set to zero. Z: Destination register COND: condition.

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19. CONDITIONAL MR STATURATION
Syntax:
IF MV SAT MR ;

Description: Test the MV (MAC Overflow) bit in the Arithmetic Status Register (ASTAT), and if set, then saturate the lower-order 32 bits of the 40-bits MR register; if the MV is not set then perform a no-operation. Saturation of MR is executed with this instruction for one cycle only; MAC saturation is not a continuous mode that is enabled or disabled. The saturation instruction is intended to be used at the completion of a series of multiply/accumulate operations so that temporary overflows do not cause the accumulator to saturate. The saturation result depends on the state of MV and on the sign of MR (the MSB of MR2). The possible results after execution of the saturation instruction are shown in the table below.
MV 0 0 1 1 MSB of MR2 0 1 0 1 MR contents after saturation No change No change 00000000 0111111111111111 1111111111111111 11111111 1000000000000000 0000000000000000

Status Generated: No status bits affected. Instruction Format:
Saturate MR operation, Instruction Type 25: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 10 1 0 00 00 00000000000
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20. ARITHMMETIC SHIFT
Syntax:
[IF cond] SR ? [SR OR ] ASHIFT xop (HI) ; (LO )

Permissible xops SI AR

Permissible conds EQ NE GT GE LT LE AC

SR1 MR2 SR0 MR1 MR0

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Example: IF LT SR = SR OR ASHIFT SI (LO); Description: Test the optional condition and, if true, then perform the designated arithmetic shift. If the condition is not true then perform a no-operation. Omitting the condition performs the shift unconditionally. The operation arithmetically shifts the bits of the operand by the amount and direction specified in the Shift Code from the SE register. Positive Shift Codes cause a left shift (upshift) and negative codes cause a right shift (downshift). The shift may be referenced to the upper half of the output field (HI option) or to the lower half (LO option). The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option. For ASHIFT with a positive Shift Code (i.e. positive value in SE), the operand is shifted left; with a negative Shift Code (i.e. negative value in SE), the operand is shifted right. The number of positions shifted is the count in the Shift Code. The 32-bit output field is sign-extended to the
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left (the MSB of the input is replicated to the left), and the output is zero-filled from the right. Bits shifted out of the high order bit in the 32-bit destination field (SR31) are dropped. Bits shifted out of the low order bit in the destination field (SR0) are dropped. To shift a double precision number, the same Shift Code is used for both halves of the number. On the first cycle, the upper half of the number is shifted using an ASHIFT with the HI option; on the following cycle, the lower half of the number is shifted using an LSHIFT with the LO and OR options. This prevents sign bit extension of the lower word‘s MSB. Status Generated: None affected. Instruction Format:
Conditional Shift operation, Instruction Type 16: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 11 0 0 SF 0100 0101 0110 0111 Shifter Function ASHIFT (HI) ASHIFT (HI,OR) ASHIFT (LO) ASHIFT(LO,OR) COND: condition SF Xop 0 0 0 0 COND

Xop: shifter operand

21. LOGICAL SHIFT
Syntax:
[IF cond] SR ? [SR OR ] LSHIFT xop (HI) ; (LO )

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61IC 中国电子在线 DSP 汇编指令集 Permissible xops SI AR Permissible conds EQ NE GT GE LT LE AC

SR1 MR2 SR0 MR1 MR0

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Example: IF GE SR = LSHIFT SI (HI); Description: Test the optional condition and, if true, then perform the designated logical shift. If the condition is not true then perform a no-operation. Omitting the condition performs the shift unconditionally. The operation logically shifts the bits of the operand by the amount and direction specified in the Shift Code from the SE register. Positive Shift Codes cause a left shift (upshift) and negative Codes cause a right shift (downshift). The shift may be referenced to the upper half of the output field (HI option) or to the lower half (LO option). The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option. For LSHIFT with a positive Shift Code, the operand is shifted left; The number of positions shifted is the count in the Shift Code. The 32-bit output field is zero-filled from the right. Bits shifted out of the high order bit in the 32-bit destination field (SR31) are dropped. For LSHIFT with a negative Shift Code, the operand is shifted right; the number of positions shifted is the count in the Shift Code. The 32-bit
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output field is zero-filled from the left. Bits shifted out of the high order bit in the 32-bit destination field (SR0) are dropped. To shift a double precision number, the same Shift Code is used for both halves of the number. On the first cycle, the upper half of the number is shifted using the HI option; on the following cycle, the lower half of the number is shifted using the LO and OR options. Status Generated: None affected. Instruction Format:
Conditional Shift operation, Instruction Type 16: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 11 0 0 SF 0000 0001 0010 0011 Shifter Function LSHIFT (HI) LSHIFT (HI,OR) LSHIFT (LO) LSHIFT (LO,OR) COND: condition SF Xop 0 0 0 0 COND

Xop: shifter operand

22. NORMALIZE
Syntax:
[IF cond] SR ? [SR OR ] NORM xop (HI) ; (LO )

Permissible xops SI AR

Permissible conds EQ NE GT GE LT LE AC

SR1 MR2 SR0 MR1 MR0

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Example: SR = NORM SI (HI);
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Description: Test the optional condition and, if true, then perform the designated normalization. If the condition is not true then perform a no-operation. Omitting the condition performs the normalize

unconditionally. The operation arithmeticall shifts the input operand to eliminate all but one of the sign bits. The amount of the shift comes from the SE register. The SE register may be loaded with the proper Shift Code to eliminate the redundant sign bits by using the Derive Exponent instruction; the Shift Code loaded will be the negative of the quantity: (the number of sign bits minus one). The shift may be referenced to the upper half of the output field (HI option) or to the lower half (LO option). The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option. When the LO reference is selected, the 32-bit output field is zero-filled to the left. Bits shifted out of the high order bit in the 32-bit destination field (SR31) are dropped. The 32-bit output field is zero-filled from the right. If the exponent of an overflowed ALU result was derived with the HIX modifier, the 32-bit output field is filled from left with the ALU Carry (AC) bit in the Arithmetic Status Register (ASTAT) during a NORM (HI) operation. In this case (SE=1 from the exponent detection on the overflowed ALU value) a downshift occurs. To normalize a double precision number, the same Shift Code is
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used for both halves of the number. On the first cycle, the upper half of the number is shifted using the HI option; on the following cycle, the lower half of the number is shifted using the LO and OR options. Status Generated: None affected. Instruction Format:
Conditional Shift operation, Instruction Type 16: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 11 0 0 SF 1000 1001 1010 1011 Shifter Function NORM (HI) NORM (HI,OR) NORM (LO) NORM (LO,OR) COND: condition SF Xop 0 0 0 0 COND

Xop: shifter operand

23. DERIVE EXPONENT
Syntax:
[IF cond] SE ? EXP xop (HI) (LO ) ; (HIX )

Permissible xops SI AR

Permissible conds EQ NE GT GE LT LE AC

SR1 MR2 SR0 MR1 MR0

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Example: IF GE SE=EXP MR1 (HI); Description: Test the optional condition and, if true, perform the designated exponent operation. If the condition is not true then perform a

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no-operation. Omitting the condition performs the exponent operation unconditionally. The EXP operation derives the effective exponent of the input operand to prepare for the normalization operation (NORM). EXP supplies the source operand to the exponent detector, which generates a Shift Code from the number of leading sign bits in the input operand. The Shift Code, stored in SE at the completion of the EXP instruction, is the effective exponent of the input value. The Shift Code depends on which exponent detector mode is used (HI, HIX, LO). In the HI mode, the input is interpreted as a single precision signed number, or as the upper half of a double precision signed number. The exponent detector counts the number of leading sign bits in the source operand and stores the resulting Shift Code in SE. The Shift Code will equal the negative of the number of redundant sign bits in the input. In the HIX mode, the input is interpreted as the result of an add or subtract which may have overflowed. HIX is intended to handle shifting and normalization of results from ALU operations. The HIX mode examines the ALU Overflow bit (AV) in the Arithmetic Status Register. If AV is set, then the effective exponent of the input is +1 (indicating that an ALU overflow occurred before the EXP operation), and +1 is stored in SE. If AV is not set, then HIX performs exactly the same operations as the HI mode.
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In the LO mode, the input is interpreted as the lower half of a double precision number. In performing the EXP operation on a double precision number, the higher half of the number must first be processed with EXP in the HI or HIX mode, and then the lower half can be processed with EXP in the LO mode. If the upper half contained a non-sign bit, then the correct Shift Code was generated in the HI or HIX operation and that is the code that is stored in SE. If, however, the upper half was all sign bits, then EXP in the LO mode totals the number or leading sign bits in the double precision word and stores the resulting Shift Code in SE. Status Generated:
A STAT: S 7 S V * SS 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

Set by the MSB of the input for an EXP operation in the HI or HIX mode with

AV=0. Set by the MSB inverted in the HIX mode with AV=1. Not affected by operations in the LO mode.

Instruction Format:
Conditional Shift Operation, Instruction Type 16: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 10 0 SF 1100 1101 1110 Shifter Function EXP(HI) EXP(HIX) EXP(LO) COND: condition.
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SF

Xop 0 0 0 0 COND

Xop: shifter operand

61IC 中国电子在线 DSP 汇编指令集

24. BLOCK EXPINENT ADJUST
Syntax:
[IF cond] SB ? EXPADJ xop;

Permissible xops SI AR

Permissible conds EQ NE GT GE LT LE AC

SR1 MR2 SR0 MR1 MR0

NEG NOT AC POS AV MV NOT MV

NOT AV NOT CE

Example: IF GT SB=EXPADJ SI; Description: Test the optional condition and, if true, perform the designated exponent operation. If the condition is not true then perform a no-operation. Omitting the condition performs the exponent operation unconditionally. The Block Exponent Adjust operation, when performed on a series of numbers, derives the effective exponent of the number largest in magnitude. This exponent can then be associated with all of the numbers in a block floating point representation. The Block Exponent Adjust circuitry applies the input operand to the exponent detector to derive its effective exponent. The input must be a signed twos complement number. The exponent detector operates in HI mode (see the EXP instruction, above). At the start of a block, the SB register should be initialized to –16 to set SB to its minimum value. On each execution of the EXPADJ instruction, the effective exponent of each operand is compared to the current contents of the SB register. If the new exponent is greater than the
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current SB value, it is written to the SB register, updating it. Therefore, at the end of the block, the SB register will contain the largest exponent found. EXPADJ is only an inspection operation; no actual shifting takes place since the true exponent is not known until all the numbers in the block have been checked. However, the numbers can be shifted at later time after the true exponent has been derived. Extended (overflowed) numbers and the lower halves of double precision numbers can not be processed with the Block Exponent Adjust instruction. Status Generated: Not affected. Instruction Format:
Conditional Shift Operation, Instruction Type 16: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 10 0 SF=1111. Xop: shifter operand COND: condition. SF Xop 0 0 0 0 COND

25. ARITHMETIC SHIFT IMMEDIATE
Syntax:
SR ? [SR OR ] ASHIFT xop BY ? exp ? (HI) ; (LO )

Permissible xops SI AR

<exp> Any constant between

SR1 MR2 SR0 MR1 MR0

–128 and 127*

Example: SR=SR OR ASHIFT SR0 BY 3 (LO); ―+3‖}
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{do not use

61IC 中国电子在线 DSP 汇编指令集

Description: Arithmetically shift the bits of the operand by the amount and direction specified by the constant in the exponent field. Positive constants cause a left shift (upshift) and negative constants cause a right shift (downshift). A positive constant must be entered without a ―+‖ sign. The shift may be referenced to the upper half of the output field (HI option) or to the lower half (LO option). The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option. For ASHIFT with a positive shift constant the operand is shifted left; with a negative shift constant the operand is shifted right. The 32-bit output field is sign-extended to the left (the MSB of the input is replicated to the left), and the output is zero-filled from the right. Bits shifted out of the high order bit in the 32-bit destination field (SR31) are dropped. Bits shifted out of the low order bit in the destination field (SR0) are dropped. To shift a double precision number, the same shift constant is used for both halves of the number. On the first cycle, the upper half of the number is shifted using an ASHIFT with the HI option; on the following cycle, the lower half is shifting using an LSHIFT with the LO and OR options. This prevents sign bit extension of the lower word‘s MSB.
*See table 2.4 in chapter 2.

Status Generated: Not affected.

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Instruction Format:
Shift Immediate Operation, Instruction Type 15: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 11 0 SF 0100 0101 0110 0111 Shifter Funciton ASHIFT (HI) ASHIFT (HI,OR) ASHIFT (LO) ASHIFT (LO,OR) SF Xop <exp>

Xop: shifter operand <exp>:8-bit signed shift value.

26. LOGICAL SHIFT IMMEDIATE
Syntax:
SR ? [SR OR ] LSHIFT xop BY ? exp ? (HI) ; (LO )

Permissible xops SI AR

<exp> Any constant between –128 and 127*

SR1 MR2 SR0 MR1 MR0

Example: SR=LSHIFT SR1 BY -6 (HI); Description: Logically shifts the bits of the operand by the amount and direction specified by the constant in the exponent field. Positive constants cause a left shift (upshift) and negative constants cause a right shift (downshift). A positive constant must be entered without a ―+‖ sign. The shift may be referenced to the upper half of the output field (HI option) or to the lower half (LO option). The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option.
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For LSHIFT with a positive shift constant the operand is shifted left. The 32-bit output field is zero-filled to the left and from the right. Bits shifted out of the high order bit in the 32-bit destination field (SR31) are dropped. For LSHIFT with a negative shift constant, the operand is shifted right. The 32-bit output field is zero-filled from the left and to the right. Bits shifted out of the low order bit in the destination field (SR0) are dropped. To shift a double precision number, the same shift constant is used for both parts of the number. On the first cycle, the upper half of the number is shifted using the HI option; on the following cycle, the lower half is shifted using the LO and OR options.
*See table 2.4 in chapter 2.

Status Generated: Not affected. Instruction Format:
Shift Immediate Operation, Instruction Type 15: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 11 0 SF 0000 0001 0010 0011 Shifter Funciton LSHIFT (HI) LSHIFT (HI,OR) LSHIFT (LO) LSHIFT (LO,OR) SF Xop <exp>

Xop: shifter operand <exp>:8-bit signed shift value.

27. REGISTER MOVE
Syntax:
reg ? reg;

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61IC 中国电子在线 DSP 汇编指令集 Permissible xops AX0 AX1 AY0 AY1 AR MR1 MR0 MX0 MX1 MY0 MY1 MR2 SI SE SB PX CNTR OWRCNTR(write only) RX0 RX1

SR1 ASTAT SR0 MSTAT

I0-I7 SSTAT(read only) TX0 TX1 IFC(write only)

M0-M7 IMASK L0-L7 ICNTL

Example: I7=AR; Description: Move the contents of the source to the destination location. The contents of the source are always right-justified in the destination location after the move. When transferring a smaller register to a large register (e.g., an 8-bit register to a 16-bit register), the value stored in the destination is either sign-extended to the left if the source is a signed value, or zero-filled to the left if the source is an unsigned value. The unsigned registers which (when used as the source) cause the value stored in the destination to be zero-filled to the left are: I0 through I7, L0 through L7, CNTR, PX, ASTAT, MSTAT, SSTAT, IMASK, and ICNTL. All other registers cause sign-extension to the left. When transferring a larger register to a smaller register (e.g., a 16-bit register to a 14-bit register), the value stored in the destination is right-justified (bit 0 maps to bit 0) and the higher-order bits are dropped. Note that whenever MR1 is loaded with data, it is sign-extended into
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MR2. Status Generated: Not affected. Instruction Format:
Internal Data Move, Instruction Type 17: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 0 1 1 01 0000 DST SRC DEST SOURCE RGP RGP REG REG

SRC REG (Source Register Group) and SOURCE REG (Source Register) select the source register according to the Register Selection Table. DST RGP (Destination Register Group) and DEST REG (Destination Register) select the destination register according to the Register Selection Table.

28. LOAD REGISTER IMMEDIATE
Syntax: reg=<data>; Dreg=<data>;
Data: <constant> ?%‘ <symbol> ?^‘ <symbol> Permissible registers: Dregs(Instruction Type 6) (16-bit load) AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR1 AY1 MY1 SR0 AR MR1 MR0 MR2 Regs(Instruction Type 7) (maximum 14-bit load) SB PX ASTAT MSTAT IMASK ICNTL I0-I7 CNTR OWRCNTR(write only) RX0 RX1 TX0 TX1 IFC(write only)

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61IC 中国电子在线 DSP 汇编指令集 M0-M7 L0-L7

Example: I0=^data_buffer; L0=%data_buffer; Description: Move the data value specified to the destination location. The data may be a constant, or any symbol referenced with the ―length of‖(%) or ―pointer to‖(^) operators. The data value is contained in the instruction word, with 16 bits for data register loads and up to 14 bits for other register loads. The value is always right-justified in the destination location after the load (bit 0 maps to bit 0). When a value of length less than the length of the destination is moved, it is sign-extended to the left to fill the destination width. Note that whenever MR1 is loaded with data, it is sign-extended into MR2. For this instruction only, the RX and TX registers may be loaded with a maximum of 14 bits of data (although the registers themselves are 16 bits wide). To load these registers with 16-bit data, use the register-to-register move instruction or the data memory-to-register move instruction with direct addressing. Status Generated: None affected. Instruction Format:
Load Data Register Immediate, Instruction Type 6: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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61IC 中国电子在线 DSP 汇编指令集 0000 DATA DREG

Data contains the immediate value to be loaded into the Data Register destination location. The data is right-justified in the field, so the value loaded into an N-bit destination register is contained in the lower-order N bits of the DATA field. DREG selects the destination Data Register for the immediate data value. One of the 16 Data Register is selected according to the DREG Selection Table. Load Non-Data register Immediate Instruction Type 7: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 RGP DATA REG

Data contains the immediate value to be loaded into the Non-Data Register destination location. The data is right-justified in the field, so the value loaded into an N-bit destination register is contained in the lower-order N bits of the DATA field. RGP (Register Group) and REG (Register) select the destination register according to the Register Selection Table.

29. DATA MEMORY READ (Direct Address)
Syntax: reg = DM(<addr>);

Permissible registers: AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR1 AY1 MY1 SR0 AR MR2 I0-I7 IMASK ICNTL TX1 IFC(write only) SB PX ASTAT MSTAT CNTR OWRCNTR(write only) RX0 RX1 TX0

MR1 M0-M7 MR0 L0-L7

Example: SI=DM(ad_port0); Description: The Read instruction moves the contents of the data memory location to the destination register. The addressing mode is direct addressing (designated by an immediate address value or by a label). The
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data memory address is stored directly in the instruction word as a full 14-bit field. The contents of the source are always right-justified in the destination register after the read (bit 0 maps bit 0). Note that whenever MR1 is loaded with data, it is sign-extended into MR2. Status Generated: None affected. Instruction Format:
Data Memory Read (Direct Address), Instruction Type 3: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 RGP ADDR REG

ADDR contains the direct address to the source location in Data Memory. RGP (Register Group) and REG (Register) select the destination register according to the Register Selection Table.

30. DATA MEMORY READ (Indirect Address)
Syntax:
I0 I1 , I2 I3 dreg ? DM( I4 I5 , I6 I7 M0 M1 M2 M3 ); M4 M5 M6 M7

Permissible dregs: AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR1 AY1 MY1 SR0 AR MR1 MR2

Example: AY0=DM(I3,M1); Description: The Data Memory Read Indirect instruction moves the
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contents of the data memory location to the destination register. The addressing mode is register indirect with post-modify. For liner (e.g. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. The contents of the source are always right- justified in the destination register after the read (bit 0 maps to bit 0). Status Generated: None affected. Instruction Format:
ALU/MAC Operation with Data Memory Read, Instruction Type 4: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 011 G 00 AMF 00000 DREG I M

AMF specifies the ALU or MAC operation to be performed in parallel with the Data Memory Read. In this case, AMF=00000, indicating a no-operation for the ALU/MAC function. DREG selects the destination Data Register. One of the 16 Data Registers is selected according to the DREG Selection Table. G specifies which Data Address Generator the I and M registers are selected from. These registers must be from the same DAG as separated by the gray bar above. I specifies the indirect address pointer (I register). M specifies the modify register (M register).

31. PROGRAM MEMORY READ (Indirect Address)
Syntax:
I4 M 4 dreg ? PM ( I5 , M5 ); I6 M 6 I7 M 7

Permissible dregs: AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR1 AY1 MY1 SR0 AR MR2
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61IC 中国电子在线 DSP 汇编指令集 MR1

Example: MX1=PM(I6,M5); Description: The Program Memory Read Indirect instruction moves the contents of the program memory location to the destination register. The addressing mode is register indirect with post-modify. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. The 16 most significant bits of the Program Memory Data bus (PMD23-8) are loaded into the destination register, with bit PMD8 lining up with bit 0 of the destination register (right-justifica –tion). If the destination register is less than 16 bits wide, the most significant bits are dropped. Bits PMD7-0 are always loaded into the PX register. You may ignore these bits or read them out on a subsequent cycle. Status Generated: None affected. Instruction Format:
ALU/MAC Operation with Program Memory Read, Instruction Type 5: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 010 1 00 AMF 00000 DREG I M

AMF specifies the ALU or MAC operation to be performed in parallel with the Data Memory Read. In this case, AMF=00000, indicating a no-operation for the ALU/MAC function. DREG selects the destination Data Register. One of the 16 Data Registers is selected according to the Register Selection Table. I specifies the indirect address pointer (I register). M specifies the modify register (M register).

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32. DATA MEMORY WRITE (Direct Address)
Syntax: DM(<addr>)=reg;
Permissible registers: AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR1 AY1 MY1 SR0 AR MR2 I0-I7 SB PX ASTAT MSTAT SSTAT(read only) TX1 CNTR OWRCNTR(write only) RX0 X1 TX0

MR1 M0-M7 MR0 L0-L7

IMASK ICNTL

Example: DM(cntl_port0)=AR; Description: Moves the contents of the source register to the data memory location specified in the instruction word. The addressing mode is direct addressing (designated by an immediate address value or by a label). The data memory address is stored directly in the instruction word as a full 14-bit field. Whenever a register less than 16 bits in length is written to memory, the value written is either sign-extended to the left if the source is a signed value, or zero-filled to the left is the source is an unsigned value. The unsigned registers which are zero –filled to the left are: I0 through I7, L0 through L7, CNTR, PX, ASTAT, MSTAT, SSTAT, IMASK, and ICNTL. All other registers are sign-extended to the left. The contents of the source are always right-justified in the destination location after the write (bit 0 maps bit 0). Note that whenever MR1 is loaded with data, it is sign-extended into
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MR2. Status Generated: None affected. Instruction Format:
Data Memory Read (Direct Address), Instruction Type 3: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 RGP ADDR REG

ADDR contains the direct address of the destination location in Data Memory. RGP (Resgister Group) and REG (Resgister) select the source register according to the Register Selection Table.

33. DATA MEMORY WRITE (Indirect Address)
Syntax:
I0 I1 , I2 I3 DM ( I4 I5 , I6 I7 M0 M1 M2 M3 ) ? dreg ; ? data ? M4 M5 M6 M7

Data: <constant> ?%‘ <symbol> ?^‘ <symbol> Permissible dregs: AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR1 AY1 MY1 SR0 AR MR1 MR0 MR2

Example: DM(I2,M0)=MR1; Description: The Data Memory Write Indirect instruction moves the contents of the source to the data memory location specified in the
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instruction word. The immediate data may be a constant or any symbol referenced with the ―length of‖ (%) or ―pointer to‖ (^) operators. The addressing mode is register indirect with post- modify. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. When a register of less than 16 bits is written to memory, the value written is sign-extended to form a 16-bit value. The contents of the source are always right-justified in the destination location after the write (bit 0 maps to bit 0). Status Generated: None affected. Instruction Format:
ALU/MAC Operation with Data Memory Write, Instruction Type 4: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 011 G 10 AMF 00000 DREG I M

Data Memory Write, Immediate Data, Instruction Type 2: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 101 G DATA I M

AMF specifies the ALU or MAC operation to be performed in parallel with the Data Memory Write. In this case, AMF=00000, indicating a no-operation for the ALU/MAC function. Data represents the actual 16-bit value. DREG selects the source Data Register. One of the 16 Data Registers is selected according to the Register Selection Table. G specifies which Data Address Generator the I and M registers are selected from. These registers must be from the same DAG as separated by the gray bar in the Syntax description above. I specifies the indirect address pointer (I register). M specifies the modify register (M register).

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34. PROGRAM MEMORY WRITE (Indirect Address)
Syntax:
I4 M 4 PM ( I5 , M5 ) ? dreg; I6 M 6 I7 M 7

Permissible dregs: AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR1 AY1 MY1 SR0 AR MR1 MR0 MR2

Example: PM(I6,M5)=AR; Description: The Program Memory Write Indirect instruction moves the contents of the source to the program memory location specified in the instruction word. The addressing mode is register indirect with post-modify. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. The 16 most significant bits of the Program Memory Data bus (PMD23-8) are loaded from the source register, with bit PMD8 aligned with bit 0 of the source register (right justification). The 8 least significant bits of the Program Memory Data bus (PMD7-0) are loaded from the PX register. Whenever a source register of length less than 16 bits is written to memory, the value written is sign-extended to form a 16-bit value. Status Generated: None affected. Instruction Format:
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61IC 中国电子在线 DSP 汇编指令集 ALU/MAC Operation with Program Memory Write, Instruction Type 5, as shown below: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 010 1 10 AMF 00000 DREG I M

AMF specifies the ALU or MAC operation to be performed in parallel with the Program Memory Write. In this case, AMF=00000, indicating a no-operation for the ALU/MAC function. DREG selects the source Data Register. One of the Data Registers is selected according to the Register Selection Table. I specifies the indirect address pointer (I register). M specifies the modify register (M register).

35. I/O SPACE READ/WRITE
(ADSP-218x only)

Syntax: IO(<addr>)=dreg; I/O write Dreg=IO(<addr>); I/O read
<addr> is an 11-bit direct address value between 0 and 2047. Permissible dregs: AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR1 AY1 MY1 SR0 AR MR1 MR0 MR2

Example: IO(23)=AX0; MY1=IO(2047); Description: The I/O space read and write instructions are used to access the ADSP-218x‘s I/O memory space. These instructions move data between the processor data registers and the I/O memory space.
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Status Generated: None affected. Instruction Format:
I/O Memory Space Read/Write, Instruction Type 29: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 0 00 01 D ADDR DREG

ADDR contains the 11-bit direct address of the source or destination location in I/O Memory Space. DREG selects the Data Register. One of the 16 Data Registers is selected according to the Register Selection Table. D specifies the direction of the transfer (0=read, 1=write).

36. JUMP
Syntax:
(I4) (I5) [IF cond]JUMP (I6) (I7) ? addr ?

;

Permissible dregs: EQ NE LE NEG GT GE LT NOT AV

POS AV

AC NOT AC

MV NOT MV NOT CE

Example: IF NOT CE JUMP top_loop; {CNTR is decremented} Description: Test the optional condition and, if true, perform the specified jump. If the condition is not true then perform a no-operation. Omitting the condition performs the jump unconditionally. The JUMP instruction causes program execution to continue at the effective address specified by the instruction. The addressing mode may be direct or register indirect. For direct addressing (using an immediate address value or a label),
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the program address is stored directly in the instruction word as a full 14-bit field. For register indirect jumps, the selected I register provides the address; it is not post-modified in this case. If JUMP is the last instruction inside a DO UNTIL loop, you must ensure that the loop stacks are properly handled. If NOT CE is used as the condition, execution of the JUMP instruction decrements the processor ‘s counter (CNTR register). Status Generated: None affected. Instruction Field:
Conditional JUMP Direct Instruction Type 10: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 1 10 ADDR COND

Conditional JUMP Indirect Instruction Type 19: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 0 1 0 1 1 0 0 0 0 0 0 0 0 I 0 0 COND

I specifies the I register (Indirect Address Pointer). ADDR: immediate jump address COND: condition

37. CALL
Syntax:
(I4) (I5) [IF cond] CALL (I6) (I7) ? addr ?

;

Permissible dregs: EQ NE LE NEG GT GE LT NOT AV

POS AV

AC NOT AC

MV NOT MV NOT CE

Example: IF AV CALL scale_down;
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Description: Test the optional condition and, if true, then perform the specified call. If the condition is not true then perform a no-operation. Omitting the condition performs the call unconditionally. The CALL instruction is intended for calling subroutines. CALL pushes the PC stack with the return address and causes program execution to continue at the effective address specified by the instruction. The addressing modes available for the CALL instruction are direct or register indirect. For direct addressing (using an immediate address value or a label), the program address is stored directly in the instruction word as a full 14-bit field. For register indirect jumps, the selected I register provides the address; it is not post-modified in this case. If CALL is the last instruction inside a DO UNTIL loop, you must ensure that the loop stacks are properly handled. Status Generated: None affected. Instruction Field:
Conditional JUMP Direct Instruction Type 10: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 1 10 ADDR COND

Conditional JUMP Indirect Instruction Type 19: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 0 10 11 0 00 00 000 I 0 0 COND

I specifies the I register (Indirect Address Pointer). ADDR: immediate jump address COND: condition

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38. JUMP or CALL ON FLAG IN PIN
Syntax:
JUMP ? addr ? ; IF FLAG _ IN NOTFLAG _ IN CALL

Example: IF FLAG_IN JUMP service_proc_three; Description: Test the condition of the FI pin of the processor and, if set to one, perform the specified jump or call. If FI is zero then perform a no-operation. Omitting the flag in condition reduces the instruction to a standard JUMP or CALL. The JUMP instruction causes program execution to continue at the address specified by the instruction. The addressing mode for the JUMP on FI must be direct. The CALL instruction is intended for calling subroutines. CALL pushes the PC stack with the return address and causes program execution to continue at the address specified by the instruction. The addressing mode for the CALL on FI must be direct. If JUMP or CALL is the last instruction inside a DO UNTIL loop, you must ensure that the loop stacks are properly handled. For direct addressing (using an immediate address value or a label), the program address is stored directly in the instruction word as a full 14-bit field. Status Generated: None affected. Instruction Field:
Conditional JUMP or CALL on Flag In Direct Instruction Type 27:

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61IC 中国电子在线 DSP 汇编指令集 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 00 0 00 1 1 Address 12LSBs S: specifies JUMP (0) or CALL (1) FIC: latched state of FI pin 1 0

Addr FIC S 2MSBs

39. MODIFY FLAG OUT PIN
Syntax:
[IF cond] SET RESET TOGGLE FLAG _ OUT FL0 FL1 FL2 [,...] ;

Example: IF MV SET FLAG_OUT, RESTE FL1; Description: Evaluate the optional condition and if true, set to one, reset to zero, or toggle the state of specified flag output pin(s). Otherwise perform a no- operation and continue with the next instruction. Omitting the condition performs the operation unconditionally. Multiple flags may be modified by including multiple clauses, separated by commas, in a single instruction. This instruction does not directly alter the flow of your program – it is provided to signal external devices. (Note that the FO pin is specified by ―FLAG_OUT‖ in the instruction syntax.) The following table shows which flag outputs are present on each ADSP-21xx processor:
Processor ADSP-2101 ADSP-2105 ADSP-2111 ADSP-2111 flag pin(s) FO FO FO FO,FL0,FL1,FL2

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61IC 中国电子在线 DSP 汇编指令集 ADSP-217x ADSP-218x ADSP-21msp5x FO,FL0,FL1,FL2 FO,FL0,FL1,FL2 FO,FL0,FL1,FL2

Status Generated: None affected. Instruction Field:
Flag Out Mode Control Instruction Type 28: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 00 00 10 0000 FL2 FO FL1 FO FL0 FO FO COND

FLAG_OUT

FO: Operation to perform on flag output pin COND: Condition code

40. RTS
Syntax: [ IF cond ] RTS;
Permissible dregs: EQ NE LE NEG GT GE LT NOT AV

POS AV

AC NOT AC

MV NOT MV NOT CE

Example: IF LE RTS; Description: Test the optional condition and, if true, then perform the specified return. If the condition is not true then perform a no-operation. Omitting the condition performs the return unconditionally. RTS executes a program return from a subroutine. The address on top of the PC stack is popped and is used as the return address. The PC stack is the only stack popped. If RTS is the last instruction inside a DO UNTIL loop, you must

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ensure that the loop stacks are properly handled. Status Generated: None affected. Instruction Field:
Condition Return, Instruction Type 20: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 COND

COND: condition.

41. RTI
Syntax: [ IF cond ] RTI;
Permissible dregs: EQ NE LE NEG GT GE LT NOT AV

POS AV

AC NOT AC

MV NOT MV NOT CE

Example: IF MV RTI; Description: Test the optional condition and, if true, then perform the specified return. If the condition is not true then perform a no-operation. Omitting the condition performs the return unconditionally. RTI executes a program return from an interrupt service routine. The address on top of the PC stack is popped and is used as the return address. The value on top of the status stack is also popped, and is loaded into the arithmetic status (ASTAT), mode status (MSTAT) and the interrupt mask (IMASK) registers. If RTI is the last instruction inside a DO UNTIL loop, you must ensure that the loop stacks are properly handled.
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Status Generated: None affected. Instruction Field:
Condition Return, Instruction Type 20: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 COND

COND: condition.

42. DO UNTIL
Syntax: DO <addr> [UNTIL term];
Permissible dregs: EQ NE LE NEG GT GE LT NOT AV FOREVER

POS AV

AC NOT AC

MV NOT MV CE

Example: DO loop_label UNTIL CE; {CNTR is decremented each pass through loop} Description: DO UNTIL sets up looping circuitry for zero-overhead looping. The program loop begins at the program instruction immediately following the DO instruction, ends at the address designated in the instruction and repeats execution until the specified termination condition is met (if one is specified) or repeats in an infinite loop (if none is specified). The termination condition is tested during execution of the last instruction in the loop, the status having been generated upon completion of the previous instruction. The address (<addr>) of the last instruction in the loop is stored directly in the instruction word. If CE is used for the termination condition, the processor ‘s counter
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(CNTR register) is decremented once for each pass through the loop. When the DO instruction is executed, the address of the last instruction is pushed onto the loop stack along with the termination condition and the current program counter value plus 1 is pushed onto the PC stack. Any nesting of DO loops continues the process of pushing the loop and PC stacks, up to the limit of the loop stack size (4 levels of loop nesting) or of the PC stack size (16 levels for subroutines plus interrupts plus loops). With either or both the loop or PC stacks full, a further attempt to perform the DO instruction will set the appropriate stack overflow bit and will perform a no-operation. Status Generated: ASTAT: Not affected.
SSTAT: 7 LSO * LSO LSE 6 LSE 0 5 SSO 4 SSE 3 CSO 2 CSE 1 PSO * 0 PSE 0

Loop Stack Overflow: set if the loop stack overflows; otherwise no affected. Loop Stack Empty: always cleared (indicating loop stack not empty)

PSO PC Stack Overflow: set if the PC stack overflows; otherwise not affected. PSE PC Stack Empty: always cleared (indicating PC stack no empty). Instruction Format: Do Until, Instruction Type 11: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 1 01 ADDR TERM

ADDR specifies the address of the last instruction in the loop. In the Instruction Syntax, this

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61IC 中国电子在线 DSP 汇编指令集 field may be a program label or an immediate address value. TERM specifies the termination condition, as shown below: TERM 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Syntax NE EQ LE GT GE LT NOT AV AV NOT AC AC POS NET NOT MV MV CE FOREVER Condition Tested Not Equal to Zero Equal Zero Less Than or Equal Zero Greater Than Zero Greater Than or Equal to Zero Less Than Zero Not ALU Overflow ALU Overflow Not ALU Carry ALU Carry X Input Sign Positive X Input Sign Negative Not MAC Overflow MAC Overflow Counter Expired Always

43. IDLE
Syntax: IDLE; IDLE (n); slow IDLE

Description: IDEL causes the processor to wait indefinitely in a low-power state, waiting for interrupts. When an interrupt occurs it is serviced and execution continues with the instruction following IDLE. Typically this next instruction will be a JUMP back to IDLE, implementing a low-power standby loop. (Note the restrictions on JUMP
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or IDLE as the last instruction in a DO UNTIL loop, detailed in Chapter 3.) IDLE(n) is a special version of IDLE that slows the processor ‘s internal clock signal to further reduce power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor n given in the instruction: n=16, 32, 64, or 128. The instruction leaves the processor fully functional, but operating at the slower rate during execution of the IDLE (n) instruction. While it is in this state, the processor ‘s other internal clock signals (such as SCLK, CLKOUT, and the timer clock) are reduced by the same ratio. When the IDLE (n) instruction is used, it slows the processor ‘s internal clock and thus its response time to incoming interrupts —the 1-cycle response time of the standard IDLE state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21xx will remain in the IDLE state for up to a maximum of n CLKIN cycles (where n=16, 32, 64 or 128) before resuming normal operation. When the IDLE(n) instruction is used in systems that have an externally generated serial clock, the serial clock rate may be faster than the processor ‘s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the IDLE state (a maximum of n CLKIN cycles).
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Serial port autobuffering continues during IDLE without affecting the idle state. Status Generated: None affected. Instruction Field:
Idle, Instruction Type 31: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 00 00 10 10 00 00 00 00 00 00 00 Slow Idle, Instruction Type 31: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 DV DV: Clock divisor

44. STACK CONTROL
Syntax: [ PUSH STS] [,POP CNTR] [,POP PC] [,POP LOOP]; POP Example: POP CNTR, POP PC, POP LOOP; Description: Stack Control pushes or pops the designated stack(s). The entire instruction executes in one cycle regardless of how many stacks are specified. The PUSH STS (Push Status Stack) instruction increments the status stack pointer by one to point to the next available status stack location; and pushes the arithmetic status (ASTAT), mode status (MSTAT), and interrupt mask register (IMASK) onto the processor ‘s status stack. Note that the PUSH STS operation is executed automatically whenever an interrupt service routine is entered. Any POP pops the value on the top of the designated stack and
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decrements the same stack pointer to the next lowest location in the stack. POP STS causes the arithmetic status (ASTAT), mode status (MSTAT), and interrupt mask (IMASK) to be popped into these same registers. This also happens automatically whenever a return from interrupt (RTI) is executed. POP CNTR causes the counter stack to be popped into the down counter. When the loop stack or PC stack is popped (with POP LOOP or POP PC, respectively), the information is lost. Returning from an interrupt (RTI) or subroutine (RTS) also pops the PC stack automatically. Status Generated:
SSTAT: 7 LSO 6 LSE * 5 SSO * 4 SSE * 3 CSO 2 CSE * 1 PSO 0 PSE *

PSE PC Stack Empty: set if a pop results in an empty program counter stack; cleared otherwise. CSE otherwise. SSE Status Stack Empty: for PUSH STS, this bit is always cleared (indicationg status stack not empty). For POP STS, SSE is set if the pop results in an empty status stack; cleared otherwise. SSO Status Stack Overflow: for PUSH STS set if the status stack overflows; otherwise no affected. LSE Loop Stack Empty: set if a pop results in an empty loop stack; cleared otherwise. Counter Stack Empty: set if a pop results in an empty counter stack; cleared

Note that once any Stack Overflow occurs, the corresponding stack overflow bit is set in SSTAT, and this bit stays set indicating there has been loss of information. Once set, the stack overflow bit can only be cleared by resetting the processor.

Instruction Format:
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61IC 中国电子在线 DSP 汇编指令集 Stack Control, Instruction Type 26: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 00 00 01 00 3 2 10

0 0 0 0 0 0 0 0 0 0 0 Pp Lp Cp Spp Lp: Loop Stack Control

Pp: PC Stack Control

Cp: Counter Stack Control Spp: Status Stack Control

45. TOPPCSTACK
A special version of the Register-to-Register Move instruction, Type 17, is provided for reading (and popping) or writing (and pushing) the top value of the PC stack. The normal POP PC instruction does not save the value popped from the stack, so to save this value into a register you must use the following special instruction: Reg = TOPPCSTACK; {pop PC stack into reg} {―toppcstack‖ may also be lowercase} The PC stack is also popped by this instruction, after a one-cycle delay. A NOP should usually be placed after the special instruction, to allow the pop to occur properly: Reg=TOPPCSTACK; NOP; {allow pop to occur correctly}

There is no standard PUSH PC instruction. To push a specific value onto the PC stack, therefore, use the following special instruction: TOPPCSTACK=reg; {push reg contents onto PC stack} The stack is pushed immediately, in the same cycle. Note that ―TOPPCSTACK‖ may not be used as a register in any

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other instruction type! Examples: AX0=TOPPCSTACK; {pop PC stack into AX0} NOP; TOPPCSTACK=I7; {push contents of I7 onto PC stack}

Only the following registers may be used in the special TOPPCSTACK instructions:
ALU, MAC, &Shifter Registers AX0 AR SI I0 I4 I1 I5 DAG Registers

M0 M4 L0 L4 M1 M5 L1 L5

AX1 MR0 SE

MX0 MR1 SR0 I2 I6 M2 M6 L2 L6 MX1 MR AY0 AY1 MY0 MY1 SR0 I3 I7 M3 M7 L3 L7

There are several restrictions on the use of the special TOPPCSTACK instructions; they are described in Chapter 3, Program Control. Instruction Format:
TOPPCSTACK=reg Internal Data Move, Instruction Type 17: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 11 01 00 00 11
SRC RGP

1111

SOURCE REG

SRC RGP (Source Register Group) and SOURCE REG (Source Register) select the source register according to the Register Selection Table.
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61IC 中国电子在线 DSP 汇编指令集 Reg=TOPPCSTACK Internal Data Move, Instruction Type 17: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 11 01 00 00
DST RGP

11

DEST REG

1111

DST RGP (Destination Register Group) and DEST REG (Destination Register) select the destination register according to the Register Selection Table.

46. MODE CONTROL
Syntax:
ENA DIS BIT _ REV AV _ LATCH AR _ SAT SEC _ REG G _ MODE M _ MODE TIMER [,...] ;

Example: DIS AR_SAT, ENA M_MODE; Description: Enables (ENA) or disables (DIS) the designated processor mode. The corresponding mode status bit in the mode status register (MSTAT) is set for ENA mode and cleared for DIS mode. At reset, MSTAT is set to zero, meaning that all modes are disabled. Any number of modes can be changed in one cycle with this instruction. Multiple ENA or DIS clauses must be separated by commas. MSTAT Bits:
0 SEC_REG 1 BIT_REV Alternate Register Data Bank Bit-Reverse Mode on Address Generator #1

2 AV_LATCH ALU Overflow Status Latch Mode 3 AR_SAT 4 M_MODE 5 TIMER 6 G_MODE ALU AR Register Saturation Mode MAC Result Placement Mode Timer Enable Enables GO Mode

The data register bank select bit (SEC_REG) determines which set
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of data register is currently active (0=primary, 1=secondary). The bit-reverse mode bit (BIT_REV), when set to1, causes addresses generated by Data Address Generator #1 to be output in bit reversed order. The ALU overflow latch mode bit (AV_LATCH), when set to 1, causes the AV bit in the arithmetic status register to stay set once an ALU overflow occurs. In this mode, if an ALU overflow occurs, the AV bit will be set and will remain set even if subsequent ALU operations do not generate overflows. The AV bit can only be cleared by writing a zero into it directly over the DMD bus. The AR saturation mode bit, (AR_SAT), when set to 1, causes the AR register to saturate if an ALU operation causes an overflow, as described in Chapter 2, ―Computation Units‖. The MAC result placement mode (M_MODE) determines whether or not the left shift is made between the multiplier product and the MR register. Setting the Timer Enable bit (TIMER) starts the timer decrementing logic. Clearing it halts the timer. The GO mode (G_MODE) allows an ADSP-21xx processor to continue executing instructions from internal memory (if possible) during a bus grant. The GO mode allows the processor to run; only if an external memory access is required does the processor halt, waiting for the bus to
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be released. Instruction Format:
Mode Control, Instruction Type 18: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 00 01 00 TI: Timer Enable AS: AR Saturation Mode Control BR: Bit Reverse Mode Control SR: Secondary Register Bank Mode TI MM AS OL BR SR GM 0 0 MM: Multiplier Placement OL: ALU Overflow Latch Mode Control GM: GO Mode

47. MODIFY ADDRESS REGISTER
I0 I1 I2 I3 ( I4 I5 I6 I7 , M0 M1 M2 M3 ); M4 M5 M6 M7

Syntax:

MODIFY

,

Example: MODIFY (I1, M1); Description: Add the selected M register M register (Mn) to the selected I register (Im), then process the modified address through the modulus logic with buffer length as determined by the L register corresponding to the selected I register (Lm), and store the resulting address pointer calculation in the selected I register. The I register is modified as if an indexed memory address were taking place, but no actual memory data transfer occurs. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. The selection of the I and M registers is constrained to registers
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within the same Data Address Generator: selection of I0-I3 in Data Address Generator #1 constrains selection of the M registers to M0-M3. Similarly, selection of I4-I7 constrains the M registers to M4-M7. Status Generated: None affected. Instruction Format:
Modify Address Register, Instruction Type 21: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 00 10 01 00 00 00 00000 GIM

G specifies which Data Address Generator is selected. The I and M registers specified must be from the same DAG, separated by the gray bar above. I specifies the I register (depends on which DAG is selected by the G bit). M specifies the M register (depends on which DAG is selected by the G bit).

48. NOP
Syntax: NOP; Description: No operation occurs for one cycle. Execution continues with the instruction following the NOP instruction. Status Generated: None affected. Instruction Format:
No operation, Instruction Type 30: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000000000000000000000000

49. INTERRUPT ENABLE & DISABLE
(ADSP-217x, ADSP-218x, ADSP-21msp58/59 only)

Syntax: ENA INTS; DIS INTS;
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Description: Interrupts are enabled by default at reset. Executing the DIS INTS instruction causes all interrupts (including the powerdown interrupt) to be masked, without changing the contents of the IMASK register. Executing the ENA INTS instruction allows all unmasked interrupts to be serviced again. Note: Disabling interrupts does not affect serial port autobuffering or ADSP-218x DMA transfers (IDMA or BDMA). These operations will continue normally whether or not interrupts are enabled. Status Generated: None affected. Instruction Format:
DIS INTS, Instruction Type 26: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000001000000000001000000 ENA INTS, Instruction Type 26: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000001000000000001100000

50. COMPUTATION with MEMORY READ
I0 I1 , I2 I3 DM ( I4 ? ALU ? I5 , ? MAC ? , dreg ? I6 ? SHIFT ? I7 I4 PM( I5 , I6 I7 M0 M1 M2 M3 ) M4 M5 ; M6 M7 M4 M5 ) M6 M7

Syntax:

Permissible dregs: AX0 MX0 SI
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61IC 中国电子在线 DSP 汇编指令集 AX1 MX1 SE AY0 MY0 SR0 AY1 MY1 SR1 AR MR1 MR2 MR0

Description: Perform the designated arithmetic operation and data transfer. The read operation moves the contents of the source to the destination register. The addressing mode when combining an arithmetic operation with a memory read is register indirect with post-modify. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. The contents of the source are always right-justified in the destination register. The computation must be unconditional. All ALU, MAC and Shifter operations are permitted except Shift Immediate and ALU DIVS and DIVQ instructions. The fundamental principle governing multifunction instructions is that registers (and memory) are read at the beginning of the processor cycle and written at the end of the cycle. The normal left-to-right order ro clauses (computation first, memory read second) is intended to imply this. In fact, you may code this instruction with the order of clauses reversed. The assembler produces a warning, but the results are identical at the opcode level. If you turn off semantics checking in the assembler (using the –s switch) the warning is not issued.
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Because of the read-first, write-second characteristic of the processor, using the same register as source in one clause and a destination in the other is legal. The register supplies the value present at the beginning of the cycle and is written with the new value at the end of the cycle. For example, (1) AR=AX0+AY0, AX0=DM(I0, M0); is a legal version of this multifunction instruction and is not flagged by the assembler. Reversing the order of clauses, as in (2) AX0=DM(I0, M0), AR=AX0+AY0; results in an assembler warning, but assembles and executes exactly as the first form of the instruction. Note that reading example (2) from left to right may suggest that the data memory value is loaded into AX0 and then used in the computation, all in the same cycle. In fact, this is not possible. The left-to-right logic of example (1) suggests the operation of the instruction more closely. Regardless of the apparent logic of reading the instruction from left to right, the read-first, write-second operation of the processor determines what actually happens. Using the same register as a destination in both clauses, however, produces an indeterminate result and should not be done. The assembler issues a warning unless semantics checking is turned off. Regardless of whether or not the warning is produced, however, this practice is not supported.
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The following, therefore, is illegal and not supported, even though assembler semantics checking produces only a warning: (3) AR=AX0+AY0, AR=DM(I0, M0); Illegal!

Status Generated: All status bits are affected in the same way as for the single function versions of the selected arithmetic operation. <ALU> operation A STAT: S 7 S V 6 M Q 5 A S 4 A C * 3 A V * 2 A N * 1 A Z * * 0 A

AZ Set if result equals zero. Cleared otherwise. AN Set if result is negative. Cleared otherwise.

AV Set if an overflow is generated. Cleared otherwise. AC Set if a carry is generated. Cleared otherwise. AS Affected only when executing the Absolute Value operation (ABS). Set if the source operand is negative. <MAC> operation A STAT: S 7 S V * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

MV Set if the accumulated product overflow the lower-order 32 bits of the MR register. Cleared otherwise. <SHIFT> operation A STAT: S 7 S V * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

SS Affected only when executing the EXP operation; set if the source operand is negative.
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61IC 中国电子在线 DSP 汇编指令集 Cleared if the number is positive.

Instruction Format:
ALU/MAC operation with Data Memory Read, Instruction Type 4: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 011 G0 Z AMF YOP XOP Dreg I M

ALU/MAC operation with Progarm Memory Read, Instruction Type 5: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 010 1 0 Z AMF YOP XOP Dreg I M

Shift operation with Data Memory Read, Instruction Type 12: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 0 1 0 01 G 0 SF XOP Dreg I M

Shift operation with Program Memory Read, Instruction Type 13: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 0 1 0 01 1 Z: Result register SF: Shifter operation Yop: Y operand G: Data Address Generator M: Modify register 0 SF XOP Dreg I M

Dreg: Destination register AMF: ALU/MAC operation Xop: X operand I: Indirect address register

51. COMPUTATION with REGISTER to REGISTER MOVE
Syntax:
? ALU ? ? MAC ? , dreg ? dreg ; ? SHIFT ?

Permissible dregs: AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR0 AY1 MY1 SR1 AR MR1
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MR0

61IC 中国电子在线 DSP 汇编指令集 MR2

Description: Perform the designated arithmetic operation and data transfer. The contents of the source are always right-justified in the destination register after the read. The computation must be unconditional. All ALU, MAC and Shifter operations are permitted except Shift Immediate and ALU DIVS and DIVQ instructions. The fundamental principle governing multifunction instruction is that registers (and memory) are read at the beginning of the processor cycle and written at the end of the cycle. The normal left-to-right order fo clauses (computation first, register transfer second) is intended to imply this. In fact, you may code this instruction with the order of clauses reversed. The assembler produces a warning, but the results are identical at the opcode level. If you turn off semantics checking in the assembler (-s switch) the warning is not issued. Because of the read-first, write-second characteristic of the processor, using the same register as source in one clause and a destination in the other is legal. The register supplies the value present at the beginning of the cycle and is written with the new value at the end of the cycle. For example, (1) AR=AX0+AY0, AX0=MR1; is a legal version of this multifunction instruction and is not flagged

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by the assembler. Reversing the order of clauses , as in (2) AX0=MR1, AR=AX0+AY0; results in an assembler warning, but assembles and executes exactly as the first form of the instruction. Note that reading example (2) from left to right may suggest that the MR1 register value is loaded into AX0 and then AX0 is used in the computation, all in the same cycle. In fact, this is not possible. The left-to-right logic of example (1) suggests the operation of instruction more closely. Regardless of the apparent logic of reading the instruction from left to right, the read-first, write-second operation of the processor determines what actually happens. Using the same register as a destination in both clauses, however, produces an indeterminate result and should not be done. The assembler issues a warning unless semantics checking is turned off. Regardless of whether or not the warning is produced, however, this practice is not supported. The following, therefore, is illegal and not supported, even though assemble semantics checking produces only a warning: (3) AR=AX0+AY0, AR=MR1; Illegal!

Status Generated: All status bits are affected in the same way as for the single function versions of the selected arithmetic operation. <ALU> operation A 7 6 5 4 3 2 1 0

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61IC 中国电子在线 DSP 汇编指令集 STAT: S S V M Q A S A C * A V * A N * A Z * * A

AZ Set if result equals zero. Cleared otherwise. AN Set if result is negative. Cleared otherwise.

AV Set if an overflow is generated. Cleared otherwise. AC Set if a carry is generated. Cleared otherwise. AS Affected only when executing the Absolute Value operation (ABS). Set if the source operand is negative. <MAC> operation A STAT: S 7 S V * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

MV Set if the accumulated product overflow the lower-order 32 bits of the MR register. Cleared otherwise. <SHIFT> operation A STAT: S 7 S V * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

SS Affected only when executing the EXP operation; set if the source operand is negative. Cleared if the number is positive.

Instruction Format:
ALU/MAC operation with Data Register Move, Instruction Type 8: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 01 0 1 Z AMF YOP XOP Dreg dest Dreg source

Shift operation with Data Register Move, Instruction Type 14:

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61IC 中国电子在线 DSP 汇编指令集 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 1 0 00 0 0 SF XOP Dreg dest Z: Result register SF: Shifter operation Yop: Y operand Dreg: Destination register AMF: ALU/MAC operation Xop: X operand Dreg source

52. COMPUTATION with MEMORY WRITE
I0 I1 , I2 I3 DM ( I4 I5 , I6 I7 I4 PM( I5 , I6 I7 M0 M1 M2 M3 ) M4 ? ALU ? M5 ? dreg , ? MAC ? ; M6 ? SHIFT ? M7 M4 M5 ) M6 M7

Syntax:

Permissible dregs: AX0 MX0 SI AX1 MX1 SE AY0 MY0 SR0 AY1 MY1 SR1 AR MR1 MR2 MR0

Description: Perform the designated arithmetic operation and data transfer. The write operation moves the contents of the source to the specified memory location. The addressing mode when combining an arithmetic operation with a memory write is register indirect with postmodify. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. The contents of the source are always right-justified in the destination register.
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The computation must be unconditional. All ALU, MAC and Shifter operations are permitted except Shift Immediate and ALU DIVS and DIVQ instructions. The fundamental principle governing multifunction instructions is that registers (and memory) are read at the beginning of the processor cycle and written at the end of the cycle. The normal left-to-right order of clauses (memory write first, computation second) is intended to imply this. In fact you may code this instruction with the order of clauses reversed. The assembler produces a warning, but the results are identical at the opcode level. If you turn off semantics checking in the assembler (-s switch) the warning is not issued. Because of the read-first, write-second characteristic of the processor, using the same register as destination in one clause and a source in the other is legal. The register supplies the value present at the beginning of the cycle and is written with the new value at the end of the cycle. For example, (1) DM(I0, M0)=AR, AR=AX0+AY0; is a legal version of this multifunction instruction and is not flagged by the assembler. Reversing the order of clauses , as in (2) AR=AX0+AY0, DM(I0, M0)=AR; results in an assembler warning, but assembles and executes exactly as the first form of the instruction. Note that reading example (2) from
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left to right may suggest that the result of the computation in AR is then written to memory, all in the same cycle. In fact, this is not possible. The left-to-right logic of example (1) suggests the operation of instruction more closely. Regardless of the apparent logic of reading the instruction from left to right, the read-first, write-second operation of the processor determines what actually happens.
Status Generated: All status bits are affected in the same way as for the single function versions of the selected arithmetic operation. <ALU> operation A STAT: S 7 S V 6 M Q 5 A S 4 A C * 3 A V * 2 A N * 1 A Z * * 0 A

AZ Set if result equals zero. Cleared otherwise. AN Set if result is negative. Cleared otherwise.

AV Set if an overflow is generated. Cleared otherwise. AC Set if a carry is generated. Cleared otherwise. AS Affected only when executing the Absolute Value operation (ABS). Set if the source operand is negative. <MAC> operation A STAT: S 7 S V * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

MV Set if the accumulated product overflow the lower-order 32 bits of the MR register. Cleared otherwise. <SHIFT> operation

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61IC 中国电子在线 DSP 汇编指令集 A STAT: S 7 S V * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

SS Affected only when executing the EXP operation; set if the source operand is negative. Cleared if the number is positive.

Instruction Format:
ALU/MAC operation with Data Memory Write, Instruction Type 4: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 11 G 1 Z AMF YOP XOP Dreg I M

ALU/MAC operation with Program Memory Write, Instruction Type 5: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 10 1 1 Z AMF Yop XOP Dreg I M

Shift operation with Data Memory Write, Instruction Type 12: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 1 0 01 G 1 SF XOP Dreg I M

Shift operation with Program Memory Write, Instruction Type 13: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00 1 0 01 1 1 Z: Result register SF: Shifter operation Yop: Y operand I: Indirect address register SF XOP Dreg I M

Dreg: Destination register AMF: ALU/MAC operation Xop: X operand operand M: Modify register

G: Data Address Generator; I & M registers must be from the same DAG, as separated by the gray bar in the Syntax description.

53. DATA & PROGRAM MEMORY READ
Syntax:
AX0 AX1 ? DM( MX 0 MX1 I0 I1 I2 I3 M0 , M1 ) , M2 M3 AY0 AY1 ? PM( MY 0 MY1 I4 I5 I6 I7 M4 , M5 ) ; M6 M7

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Description: Perform the designated memory reads, one from data memory and one from program memory. Each read operation moves the contents of the memory location to the destination register. For this double data fetch, the destinations for data memory reads are the X registers in the ALU and the MAC, and the destinations for program memory reads are the Y registers. The addressing mode for this memory read is register indirect with post-modify. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. The contents of the source are always right-justified in the destination register. A multifunction instruction requires three items to be fetched from memory: the instruction itself and two data words. No extra cycle is needed to execute the instruction as long as only one of the fetches is from external memory. If two off-chip accesses are required, however—the instruction fetch and one data fetch, for example, or data fetches from both program and data memory—then one overhead cycle occurs. In this case the program memory access occurs first, then the data memory access. If three off-chip accesses are required—the instruction fetch as well as data fetches from both program and data memory—then two overhead cycles occur. Status Generated: No status bits are affected.
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Instruction Format:
ALU/MAC with Data & Program Memory Read, Instruction Type 1: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 1 1 PD DD AMF 32 10

0 0 0 0 0 PM PM DM DM I M I M

AMF specifies the ALU or MAC function. In this case, AMF=00000, designating a no-operation for the ALU or MAC function. PD: Program Destination register AMF: ALU/MAC operation M: Modify register DD: Data Destination register I: Indirect address register

54. ALU/MAC with DATA & PROGRAM MEMORY READ
Syntax:
AX0 ? AUL ? , AX1 ? DM( ? MAC ? MX 0 MX1 I0 I1 I2 I3 M0 , M1 ), M2 M3 AY0 AY1 ? PM( MY 0 MY1 I4 I5 I6 I7 M4 , M5 ) ; M6 M7

Description: This instruction combines an ALU or a MAC operation with a data memory read and a program memory read. The read operations move the contents of the memory location to the destination register. For this double data fetch, the destinations for data memory reads are the X registers in the ALU and the MAC, and the destinations for program memory reads are the Y registers. The addressing mode is register indirect with post-modify. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. The contents of the source are always right-justified in the destination register after the read. A multifunction instruction requires three items to be fetched from memory: the instruction itself and two data words. No extra cycle is
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61IC 中国电子在线 DSP 汇编指令集

needed to execute the instruction as long as only one of the fetches is from external memory. If two off-chip accesses are required, however—the instruction fetch and one data fetch, for example, or data fetches from both program and data memory—then one overhead cycle occurs. In this case the program memory access occurs first, then the data memory access. If three off-chip accesses are required—the instruction fetch as well as data fetches from both program and data memory—then two overhead cycles occur. The computation must be unconditional. All ALU and MAC operations are permitted except the DIVS and DIVQ instructions. The results of the computation must be written into the R register of the computational unit; ALU results to AR, MAC results to MR. The fundamental principle governing multifunction instructions is that registers (and memory) are read at the beginning of the processor cycle and written at the end of the cycle. The normal left-to-right order of clauses (computation first, memory reads second) is intended to imply this. In fact, you may code this instruction with the orderof clauses altered. The assembler produces a warning, but the results are identical at the opcode level. If you turn off semantics checking in the assemble (-s switch) the warning is not issued. The same data register may be used as a source for the arithmetic
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61IC 中国电子在线 DSP 汇编指令集

operation and as a destination for the memory read. The register supplies the value present at the beginning of the cycle and is written with the value from memory at the end of the cycle. For example, (1) MR=MR+MX0*MY0(UU), MX0=DM(I0, M0), MY0=PM(I4, M4); is a legal version of this multifunction instruction and is not flagged by the assembler. Changing the order of clauses, as in (2) MX0=DM(I0, M0), MY0=PM(I4, M4) ,

MR=MR+MX0*MY0(UU); results in an assembler warning, but assembles and executes exactly as the first form of the instruction. Note that reading example (2) from left to right may suggest that the data memory value is loaded into MX0 and MY0 and subsequently used in the computation, all in the same cycle. In fact, this is not possible. The left-to-right logic of example (1) suggests the operation of the instruction more closely. Regardless of the apparent logic of reading the instruction from left to right, the read-first, write-second operation of the processor determines what actually happens.
Status Generated: All status bits are affected in the same way as for the single operation version of the selected arithmetic operation. <ALU> operation A 7 6 5 4 3 2 1 0

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61IC 中国电子在线 DSP 汇编指令集 STAT: S S V M Q A S A C * A V * A N * A Z * * A

AZ Set if result equals zero. Cleared otherwise. AN Set if result is negative. Cleared otherwise.

AV Set if an overflow is generated. Cleared otherwise. AC Set if a carry is generated. Cleared otherwise. AS Affected only when executing the Absolute Value operation (ABS). Set if the source operand is negative. <MAC> operation A STAT: S 7 S V * 6 M Q 5 A S 4 A C 3 A V 2 A N 1 A Z 0 A

MV Set if the accumulated product overflow the lower-order 32 bits of the MR register. Cleared otherwise.

Instruction Format:
ALU/MAC with Data and Program Memory Read, Instruction Type 1: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 1 1 PD DD AMF 32 10

Yop Xop PM PM DM DM I M I M

PD: Program Destination register AMF: ALU/MAC operation Yop: Y operand I: Indirect address register

DD: Data Destination register M: Modify register X: X operand

55. 附录
A. Table 15.1
Table 15.1 Summary Of Valid Combinations For Multifunction Instructions

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61IC 中国电子在线 DSP 汇编指令集 Data Move Data Move Unconditional Computations (DM=DAG1) G2) None or any ALU (except Division) or MAC
Any ALU except Division ? ? Any MAC ? Any Shifter except Im mediate ? ?

(PM=DA

DM read

PM read

DM read ? ? ? ? PM read ? ? DM write ? ? ? ? PM write ? ? ?Re gister ? To ? Re gister

B. Table 15.2 Table 15.2 Multifunction instructions
? ALU ?* ? ? MAC ?
*?

,

AX0 AX1 MX 0 MY1 , , , ,

? DM( I0 I1 I2 I3

, , , ,

M0 ) , M1 M2 M3 ? PM( I4 I5 I6 I7

AY0 AY1 MY 0 MY1 , , , ,

? PM( I4 I5 I6 I7

, , , ,

M4 ) ; M5 M6 M7

AX0 AX1 MX 0 MY1

? DM( I0 I1 I2 I3

M0 ) , M1 M2 M3

AY0 AY1 MY 0 MY1

M4 ) ; M5 M6 M7

DM ( ? ALU ? * ? MAC ? * , dreg ? ? SHIFT ? * PM(

I0 I1 , I2 I3 I4 I5 , I6 I7 I4 I5 , I6 I7

M0 M1 M2 M3 M4 M5 M6 M7 M4 M5 M6 M7

) ;

)

I0 I1 , I2 I3 DM ( I4 I5 , I6 I7 I4 PM( I5 , I6 I7

M0 M1 M2 M3 ) M4 ? ALU ? * M5 ? dreg , ? MAC ? * ; M6 ? SHIFT ? * M7 M4 M5 ) M6 M7

? ALU ? * ? MAC ? * , dreg ? dreg ; ? SHIFT ? *

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61IC 中国电子在线 DSP 汇编指令集

C. Table 15.3 Table 15.3 ALU Instructions
[IF cond] | AR | ? xop | ? yop | AF | | ?C | ? yop ? C | ?cons tan t | | | | | | | | | | ; | | | ; ;

| ?cons tan t ? C | [IF cond] | AR | ? xop | ? yop | AF | | ? yop? C ? 1 | ?C ? 1 | ?cons tan t

| ?cons tan t ? C ? 1 | [IF cond] | AR | ? | yop ? | xop | AF | | | | |
AR AF

? | xop ? C ? 1 | ? xop ? C ? 1 ? xop ? cons tan t

? xop ? cons tan t ? C ? 1 |
yop ; cons tan t

[IF cond]

AND ? xop OR XOR

[IF cond]

AR AF

?

TSTBIT n OF xop SETBIT n OF xop ; CLRBIT n OF xop TGLBIT n OF xop
xop yop ; constan t

[IF cond]

AR AF

? PASS

[IF cond]

AR AF AR AF AR AF AR AF AR AF

? ?

xop ; yop xop ; yop

[IF cond]

?

NOT

[IF cond]

? ABS xop ;

[IF

cond]

?

yop ? 1 ;

[IF cond]

?

yop ? 1 ;

DIVS yop , xop ; DIVQ xop ;

NONE ? ? ALU ? ;

D. Table 15.4 Table 15.4 MAC Instructions

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61IC 中国电子在线 DSP 汇编指令集

[IF cond]

MR MF

(SS) (SU ) xop ? xop ? ( US) ; yop ( UU ) (RND)

[IF

cond]

MR MF

?

(SS) (SU) xop MR ? xop ? ( US) ; yop ( UU ) (RND)

[IF cond]

MR MF

(SS) (SU) xop ? MR ? xop ? ( US) ; yop ( UU ) (RND)

[IF cond]

MR MF MR MF

? 0 ;

[IF cond]

? MR [( RND)] ;

IF MV SAT MR ;

E. Table 15.5 Table 15.5 Shifter Instructions
[IF cond] SR ? [SR OR ] ASHIFT xop (HI) ; (LO ) xop (HI) ; (LO )

[IF cond] SR ? [SR

OR ] LSHIFT

[IF cond] SR ? [SR

OR ] NORM xop (HI) ; (LO )

[IF cond] SE ? EXP

xop

(HI) (LO ) ; (HIX )

[IF cond] SB ? EXPADJ xop;
SR ? [SR OR ] ASHIFT xop BY ? exp ? (HI) ; (LO ) (HI) ; (LO )

SR

?

[SR

OR ] LSHIFT

xop BY ? exp ?

F. Table 15.6 Table 15.6 MOVE Instructions
reg ? reg;

reg=<data>;

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61IC 中国电子在线 DSP 汇编指令集

reg = DM(<addr>);
I0 I1 , I2 I3 dreg ? DM( I4 I5 , I6 I7 M0 M1 M2 M3 ); M4 M5 M6 M7

I4 M 4 dreg ? PM ( I5 , M5 ); I6 M 6 I7 M 7

DM(<addr>)=reg;
I4 dreg ? PM( I5 , I6 I7 I4 PM( I5 , I6 I7 M4 M5 ); M6 M7

M4 M5 ) ? dreg; M6 M7

G. Table 15.7 Table 15.7 Processor Registers: reg & dreg Registers: reg
SB PX I0-I7, M0-M7, L0-L7 CNTR ASTAT, MSTAT, SSTAT IMASK, ICNTL, IFC TX0, TX1, RX0, RX1 Data Registers: dreg AX0, AX1, AY0, AY1, AR MX0, MX1, MY0, MY1, MR0, MR1, MR2 SI, SE, SR0, SR1

H. Table 15.8 Table 15.8 Program Flow Control Instructions
(I4) (I5) [IF cond]JUMP (I6) (I7) ? addr ?
JUMP ? addr ? ; IF FLAG _ IN NOTFLAG _ IN CALL

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61IC 中国电子在线 DSP 汇编指令集

(I4) (I5) [IF cond] CALL (I6) (I7) ? addr ?

[ IF cond ] RTS; [ IF cond ] RTI; DO <addr> [UNTIL termination]; IDLE (n); I. Table 15.9 Table 15.9 IF Condition Codes
Syntax EQ NE LT GE LE GT AC NOT AC AV NOT AV MV NOT MV NEG POS NOT CE FLAG_IN* NOT Status Condition Equal Zero Not Equal Zero Less Than Zero Greater Than or Equal Zero Less Than or Equal Zero Greater Than Zero ALU Carry Not ALU Carry ALU Overflow Not ALU Overflow MAC Overflow Not MAC Overflow X Input Sign Negative X Input Sign Positive Not Counter Expired FI pin Not FI pin Last sample of FI pin =1 Last sample of FI pin =0 True If AZ=1 AZ=0 AN.XOR.AV=1 AN.XOR.AN=0 (AN.XOR.AV).OR.AZ=1 (AN.XOR.AV).OR.AZ=0 AC=1 AC=0 AV=1 AV=0 MV=1 MV=0 AS=1 AS=0

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61IC 中国电子在线 DSP 汇编指令集 FLAG_IN*

J. Table 15.10 Table 15.10 Miscellaneous Instructions NOP; [ PUSH STS] [,POP CNTR] [,POP PC] [,POP LOOP]; POP
ENA DIS BIT _ REV AV _ LATCH AR _ SAT SEC _ REG G _ MODE M _ MODE TIMER

[,...] ;

MODIFY

I0 I1 I2 I3 ( I4 I5 I6 I7

,

,

M0 M1 M2 M3 ); M4 M5 M6 M7

[IF cond]

SET RESET TOGGLE

FLAG _ OUT FL0 FL1 FL2

[,...] ;

ENA INTS; DIS INTS; 21IC 中国电子在线 http://www.21ic.com 21IC 工程师社区 http://www.21icbbs.com 中国最大的 DSP 专业技术资料网站,大量 DSP 资料下载和技术文 章

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